Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 274 of 926
REJ09B0283-0300
• DMABCRL
Bit Bit Name Initial Value R/W Description
7
6
5
4
DTE1B
DTE1A
DTE0B
DTE0A
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Enable 1B
Data Transfer Enable 1A
Data Transfer Enable 0B
Data Transfer Enable 0A
If the DTIE bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a
transfer, and issues a transfer end interrupt
request to the CPU or DTC.
When DTE = 1, data transfer is enabled and the
DMAC waits for a request by the activation
source selected by the DTF3 to DTF0 bits in
DMACR. When a request is issued by the
activation source, DMA transfer is executed.
[Clearing conditions]
• When initialization is performed
• When the specified number of transfers
have been completed in a transfer mode
other than repeat mode
• When 0 is written to the DTE bit to forcibly
suspend the transfer, or for a similar reason
[Setting condition]
When 1 is written to the DTE bit after reading
DTE = 0
3
2
1
0
DTIE1B
DTIE1A
DTIE0B
DTIE0A
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer End Interrupt Enable 1B
Data Transfer End Interrupt Enable 1A
Data Transfer End Interrupt Enable 0B
Data Transfer End Interrupt Enable 0A
These bits enable or disable an interrupt to the
CPU or DTC when transfer ends. If the DTIE bit
is set to 1 when DTE = 0, the DMAC regards
this as indicating the end of a transfer, and
issues a transfer end interrupt request to the
CPU or DTC.
A transfer end interrupt can be canceled either
by clearing the DTIE bit to 0 in the interrupt
handling routine, or by performing processing to
continue transfer by setting the transfer counter
and address register again, and then setting the
DTE bit to 1.