To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/36049 Group 16 Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series H8/36049F H8/36049 H8/36048 H8/36047 HD64F36049, HD64F36049G, HD64336049, HD64336049G, HD64336048, HD64336048G, HD64336047, HD64336047G Rev.3.00 2006.
Rev. 3.00 Mar.
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface The H8/36049 Group comprises single-chip microcomputers made up of the high-speed H8/300H CPU as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/36049 Group in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
Notes: When using an on-chip emulator (E7 or E8) for H8/36049 Group program development and debugging, the following restrictions must be noted. The NMI pin is reserved for the E7 or E8, and cannot be used. Pins P85, P86, and P87 cannot be used. Area H'FFF780 to H'FFFB7F must on no account be accessed. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8.
Application notes: Document Title Document No. H8S, H8/300 Series C/C++ Compiler Package Application Note TM Single Power Supply F-ZTAT On-Board Programming Rev. 3.00 Mar.
Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features................................................................................................................................. 1 Internal Block Diagram......................................................................................................... 3 Pin Arrangement ....................................................................................
3.3 3.4 3.5 3.2.4 Interrupt Enable Register 2 (IENR2) .................................................................. 50 3.2.5 Interrupt Flag Register 1 (IRR1)......................................................................... 50 3.2.6 Interrupt Flag Register 2 (IRR2)......................................................................... 52 3.2.7 Wakeup Interrupt Flag Register (IWPR) ............................................................ 53 Reset Exception Handling .......................
Section 6 Power-Down Modes ............................................................................75 6.1 6.2 6.3 6.4 6.5 Register Descriptions.......................................................................................................... 75 6.1.1 System Control Register 1 (SYSCR1) ................................................................ 76 6.1.2 System Control Register 2 (SYSCR2) ................................................................ 77 6.1.
Section 8 RAM .................................................................................................. 109 Section 9 I/O Ports............................................................................................. 111 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 Port 1................................................................................................................................. 111 9.1.1 Port Mode Register 1 (PMR1) ................................................................
9.9 Port B ................................................................................................................................ 145 9.9.1 Port Data Register B (PDRB) ........................................................................... 145 Section 10 Realtime Clock (RTC) .....................................................................147 10.1 10.2 10.3 10.4 10.5 Features...............................................................................................................
12.4 12.5 12.6 12.3.4 Timer Control/Status Register V (TCSRV) ...................................................... 170 12.3.5 Timer Control Register V1 (TCRV1) ............................................................... 172 Operation .......................................................................................................................... 173 12.4.1 Timer V Operation............................................................................................
14.4 14.5 14.6 14.3.2 Timer Mode Register (TMDR) ......................................................................... 221 14.3.3 Timer PWM Mode Register (TPMR) ............................................................... 222 14.3.4 Timer Function Control Register (TFCR)......................................................... 223 14.3.5 Timer Output Master Enable Register (TOER) ................................................ 225 14.3.6 Timer Output Control Register (TOCR) ......................
16.4 16.3.1 PWM Control Register (PWCR) ...................................................................... 296 16.3.2 PWM Data Registers U, L (PWDRU, PWDRL) .............................................. 297 Operation .......................................................................................................................... 297 Section 17 Serial Communication Interface 3 (SCI3)....................................... 299 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 Features..............
Section 18 I2C Bus Interface 2 (IIC2) ................................................................341 18.1 18.2 18.3 18.4 18.5 18.6 18.7 Features............................................................................................................................. 341 Input/Output Pins.............................................................................................................. 343 Register Descriptions.............................................................................
19.5 19.6 19.4.4 External Trigger Input Timing.......................................................................... 386 A/D Conversion Accuracy Definitions ............................................................................. 387 Usage Notes ...................................................................................................................... 390 19.6.1 Permissible Signal Source Impedance .............................................................. 390 19.6.
23.4 23.5 23.3.4 A/D Converter Characteristics .......................................................................... 456 23.3.5 Watchdog Timer Characteristics....................................................................... 457 23.3.6 Power-Supply-Voltage Detection Circuit Characteristics (Optional) ............... 458 23.3.7 Power-On Reset Circuit Characteristics (Optional) .......................................... 459 Operation Timing...........................................................
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Figures Section 1 Overview Figure 1.1 Internal Block Diagram ................................................................................................. 3 Figure 1.2 Pin Arrangements (FP-80A).......................................................................................... 4 Section 2 CPU Figure 2.1 Memory Map............................................................................................................... 10 Figure 2.2 CPU Registers ...............................................
Figure 5.7 Block Diagram of Subclock Generator ....................................................................... 72 Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator................................................ 72 Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 72 Figure 5.10 Pin Connection when not Using Subclock ................................................................ 73 Figure 5.
Figure 12.8 Clear Timing by TMRIV Input ............................................................................... 176 Figure 12.9 Pulse Output Example ............................................................................................. 176 Figure 12.10 Example of Pulse Output Synchronized to TRGV Input....................................... 177 Figure 12.11 Contention between TCNTV Write and Clear ...................................................... 178 Figure 12.
Figure 14.3 Timer Z (Channel 1) Block Diagram ...................................................................... 217 Figure 14.4 Example of Outputs in Reset Synchronous PWM Mode and Complementary PWM Mode............................................................................................................. 224 Figure 14.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits))........ 236 Figure 14.6 Accessing Operation of 8-Bit Register (between CPU and TSTR (8 bits)) ............
Figure 14.38 Example of Buffer Operation (1) (Buffer Operation for Output Compare Register).................................................. 270 Figure 14.39 Example of Compare Match Timing for Buffer Operation ................................... 271 Figure 14.40 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register) ...................................................... 272 Figure 14.41 Input Capture Timing of Buffer Operation.........................................................
Figure 17.4 Sample SCI3 Initialization Flowchart ..................................................................... 319 Figure 17.5 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 320 Figure 17.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 321 Figure 17.7 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ..................
Figure 18.17 Figure 18.18 Figure 18.19 Figure 18.20 Figure 18.21 Section 19 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.4 Figure 19.5 Sample Flowchart for Master Transmit Mode....................................................... 369 Sample Flowchart for Master Receive Mode ........................................................ 370 Sample Flowchart for Slave Transmit Mode......................................................... 371 Sample Flowchart for Slave Receive Mode ..................
Figure B.8 Port 2 Block Diagram (P22) ..................................................................................... 498 Figure B.9 Port 2 Block Diagram (P21) ..................................................................................... 498 Figure B.10 Port 2 Block Diagram (P20) ................................................................................... 499 Figure B.11 Port 3 Block Diagram (P37 to P30) ........................................................................
Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 5 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 18 Table 2.2 Data Transfer Instructions....................................................................................... 19 Table 2.3 Arithmetic Operations Instructions (1) ...............................
Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible................................................................................................................... 98 Reprogram Data Computation Table .................................................................... 102 Additional-Program Data Computation Table ...................................................... 102 Programming Time ...................................
Table 17.5 Table 17.5 Table 17.6 Table 17.7 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) .......................................................................................................................... 316 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) .......................................................................................................................... 317 SSR Status Flags and Receive Data Handling .............
Appendix Table A.1 Table A.2 Table A.2 Table A.2 Table A.3 Table A.4 Table A.5 Instruction Set....................................................................................................... 465 Operation Code Map (1) ....................................................................................... 478 Operation Code Map (2) ....................................................................................... 479 Operation Code Map (3) ........................................................
Section 1 Overview Section 1 Overview 1.
Section 1 Overview • General I/O ports I/O pins: 59 I/O pins, including 13 large current ports (IOL = 20 mA, @VOL = 1.5 V) Input-only pins: 8 input pins (also used for analog input) • Supports various power-down modes • Compact package Package Code Body Size Pin Pitch QFP-80 FP-80A 14.0 × 14.0 mm 0.65 mm Rev. 3.00 Mar.
Section 1 Overview Subclock generator NMI TEST RES VSS VSS VCC Port 6 Port 7 P77 P76/TMOV P75/TMCIV P74/TMRIV P72/TXD_2 P71/RXD_2 P70/SCK3_2 Port 8 P87 P86 P85 P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI Port 9 RAM ROM P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 P97 P96 P95 P94 P93 P92/TXD_3 P91/RXD_3 P90/SCK3_3 IIC2 RTC SCI3 14-bit PWM SCI3_2 Timer Z SCI3_3 Timer V Watchdog timer Timer W Timer B1 A/D converter POR and LVD (option)
Section 1 Overview P20/SCK3 P60/FTIOA0 P61/FTIOB0 P62/FTIOC0 P63/FTIOD0 P64/FTIOA1 P65/FTIOB1 P66/FTIOC1 P67/FTIOD1 Vss P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P10/TMOW P11/PWM P12 P90/SCK3_3 Pin Arrangement P91/RXD_3 1.
Section 1 Overview 1.4 Pin Functions Table 1.1 Pin Functions Pin No. Type Symbol FP-80A I/O Functions Power supply pins Vcc 12 Input Power supply pin. Connect this pin to the system power supply. Vss 9, 50 Input Ground pin. Ensure to connect all pins to the system power supply (0 V). AVcc 3 Input Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. AVss 74 Input Analog ground pin for the A/D converter.
Section 1 Overview Pin No. Type Symbol FP-80A I/O Timer V TMOV 72 Output This is an output pin for waveforms generated by the output compare function. TMCIV 71 Input External event input pin. TMRIV 70 Input Counter reset input pin. TRGV 28 Input Count start trigger input pin.
Section 1 Overview Pin No.
Section 1 Overview Rev. 3.00 Mar.
Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only advanced mode, which has a 16-Mbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added.
Section 2 CPU • Power-down state Transition to power-down state by SLEEP instruction 2.1 Address Space and Memory Map The address space of this LSI is 16 Mbytes, which includes the program area and data area. Figure 2.1 shows the memory map.
Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR).
Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Empty area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
Section 2 CPU Bit Initial Bit Name Value R/W Description 7 I R/W Interrupt Mask Bit 1 Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.
Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers.
Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data 0 LSB 0 LSB ERn 31 16 15 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 3.00 Mar.
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.4 Instruction Set 2.4.1 List of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.
Section 2 CPU Symbol Description :3/:8/:16/:24 3-, 8-, 16-, or 24-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ~ ( of ) → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd) Transfers the CCR contents to a destination location.
Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction.
Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.4, Combinations of Instructions and Addressing Modes. Arithmetic and logic instructions can use the register direct and immediate modes.
Section 2 CPU Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand. A 16-bit displacement is sign-extended when added.
Section 2 CPU Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address.
Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, a 24-bit effective address is generated. Table 2.12 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents.
Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op 0 H'FFFF abs @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 23 0 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states.
Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For details on the data bus width and number of accessing states of each register, refer to section 22, List of Registers. Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size.
Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes.
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Interrupt source Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.12 State Transitions 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
Section 2 CPU 2.8.3 Bit Manipulation Instruction The BSET, BCLR, BNOT, BST, and BIST instructions read data from the specified address in byte units, manipulate the data of the target bit, and write data to the same address again in byte units.
Section 2 CPU Example 2: The BSET instruction is executed for port 5. P57 and P56 are input pins, with a low-level signal input at P57 and a high-level signal input at P56. P55 to P50 are output pins and output low-level signals. An example to output a high-level signal at P50 with a BSET instruction is shown below.
Section 2 CPU • Description on operation 1. When the BSET instruction is executed, first the CPU reads port 5. Since P57 and P56 are input pins, the CPU reads the pin states (low-level and high-level input). P55 to P50 are output pins, so the CPU reads the value in PDR5. In this example PDR5 has a value of H'80, but the value read by the CPU is H'40. 2. Next, the CPU sets bit 0 of the read data to 1, changing the PDR5 data to H'41. 3.
Section 2 CPU • After executing BSET instruction MOV.B MOV.B @RAM0, R0L R0L, @PDR5 The work area (RAM0) value is written to PDR5.
Section 2 CPU • After executing BCLR instruction P57 P56 P55 P54 P53 P52 P51 P50 Input/output Output Output Output Output Output Output Output Input Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 1 1 1 1 1 1 1 0 PDR5 1 0 0 0 0 0 0 0 • Description on operation 1. When the BCLR instruction is executed, first the CPU reads PCR5.
Section 2 CPU • BCLR instruction executed BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area (RAM0). • After executing BCLR instruction MOV.B MOV.B @RAM0, R0L R0L, @PCR5 P57 P56 The work area (RAM0) value is written to PCR5.
Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin.
Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.
Section 3 Exception Handling Relative Module Exception Sources Vector Number RTC Overflow Reserved for system use Vector Address Priority 19 H'00004C to H'00004F High 20 H'000050 to H'000053 Timer W Input capture A/compare match A 21 Input capture B/compare match B Input capture C/compare match C Input capture D/compare match D Overflow H'000054 to H'000057 Timer V Compare match A Compare match B Overflow 22 H'000058 to H'00005B SCI3 Receive data full Transmit data empty Transmit en
Section 3 Exception Handling Relative Module Exception Sources Vector Number Reserved for system use SCI3_3 Receive data full Transmit data empty Transmit end Receive error Note: 3.2 * Priority 33 H'000084 to H'000087 High 34 H'000088 to H'00008B Low A low-voltage detection interrupt is enabled only in the product with an on-chip poweron reset and low-voltage detection circuit. Register Descriptions Interrupts are controlled by the following registers.
Section 3 Exception Handling 3.2.1 Interrupt Edge Select Register 1 (IEGR1) IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to IRQ0. Bit Bit Name Initial Value R/W Description 7 NMIEG 0 R/W NMI Edge Select 0: Falling edge of NMI pin input is detected 1: Rising edge of NMI pin input is detected 6 1 Reserved 5 1 These bits are always read as 1.
Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Bit Bit Name Initial Value R/W Description 7 1 Reserved 6 1 These bits are always read as 1.
Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, RTC interrupts, and external pin interrupts. Bit Bit Name Initial Value R/W Description 7 IENDT 0 R/W Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6 IENTA 0 R/W RTC Interrupt Enable When this bit is set to 1, RTC interrupt requests are enabled.
Section 3 Exception Handling 3.2.4 Interrupt Enable Register 2 (IENR2) IENR2 enables, timer B1 overflow interrupts. Bit Bit Name Initial Value R/W Description 7 0 Reserved 6 0 These bits are always read as 0. 5 IENTB1 0 R/W Timer B1 Interrupt Enable When this bit is set to 1, timer B1 overflow interrupt requests are enabled. 4 1 Reserved 3 1 These bits are always read as 1.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 6 IRRTA R/W RTC Interrupt Request Flag [Setting condition] When the RTC counter value overflows [Clearing condition] When IRRTA is cleared by writing 0 5 1 Reserved 4 1 These bits are always read as 1. 3 IRRI3 0 R/W IRQ3 Interrupt Request Flag [Setting condition] When IRQ3 pin is designated for interrupt input and the designated signal edge is detected.
Section 3 Exception Handling 3.2.6 Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 overflow interrupts. Bit Bit Name Initial Value R/W Description 7 0 Reserved 6 0 These bits are always read as 0. 5 IRRTB1 0 R/W Timer B1 Interrupt Request flag [Setting condition] When the timer B1 counter value overflows [Clearing condition] When IRRTB1 is cleared by writing 0 4 1 Reserved 3 1 These bits are always read as 1.
Section 3 Exception Handling 3.2.7 Wakeup Interrupt Flag Register (IWPR) IWPR is a status flag register for WKP5 to WKP0 interrupt requests. Bit Bit Name Initial Value R/W Description 7 1 Reserved 6 1 These bits are always read as 1. 5 IWPF5 0 R/W WKP5 Interrupt Request Flag [Setting condition] When WKP5 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF5 is cleared by writing 0.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 0 IWPF0 0 R/W WKP0 Interrupt Request Flag [Setting condition] When WKP0 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF0 is cleared by writing 0. 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset.
Section 3 Exception Handling 3.4 Interrupt Exception Handling 3.4.1 External Interrupts As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts. NMI Interrupt: NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1. NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit value in CCR.
Section 3 Exception Handling WKP5 to WKP0 Interrupts: WKP5 to WKP0 interrupts are requested by input signals to pins WKP5 to WKP0. These six interrupts have the same vector addresses, and are detected individually by either rising edge sensing or falling edge sensing, depending on the settings of bits WPEG5 to WPEG0 in IEGR2.
Section 3 Exception Handling 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag to show the interrupt request status and the enable bit to enable or disable the interrupt. For RTC interrupt requests and direct transfer interrupt requests generated by execution of a SLEEP instruction, this function is included in IRR1, IRR2, IENR1, and IENR2.
Section 3 Exception Handling Figure 3.3 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM.
Section 3 Exception Handling 3.4.4 Interrupt Response Time Table 3.2 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handling-routine is executed. Table 3.2 Interrupt Wait States Item States 1 Interrupt priority determination 2* 2 Total 19 to 41 Waiting time for completion of executing instruction* 1 to 23 Saving of PC and CCR to stack 4 Vector fetch 4 Instruction fetch 4 Internal processing 4 Notes: 1.
REJ09B0060-0300 Rev. 3.00 Mar. 15, 2006 Page 60 of 526 Internal data bus Figure 3.
Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Section 3 Exception Handling CCR I bit ← 1 Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.) Set port mode register bit Execute NOP instruction After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0. Clear interrupt request flag to 0 CCR I bit ← 0 Interrupt mask cleared Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure Rev.
Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Section 4 Address Break 4.1 Register Descriptions The address break has the following registers. • • • • Address break control register (ABRKCR) Address break status register (ABRKSR) Break address registers E, H, L (BARE, BARH, BARL) Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions.
Section 4 Address Break Bit Bit Name Initial Value R/W Description 1 DCMP1 0 R/W Data Compare 1 and 0 0 DCMP0 0 R/W These bits set the comparison condition between the data set in BDR and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDRL and data bus 10: Compares upper 8-bit data between BDRH and data bus 11: Compares 16-bit data between BDR and data bus [Legend] x: Don't care.
Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Bit Bit Name Initial Value R/W Description 7 ABIF 0 R/W Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR is satisfied [Clearing condition] When 0 is written after ABIF=1 is read 6 ABIE 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled.
Section 4 Address Break 4.2 Operation When the ABIE bit in ABRKSR is set to 1, if the ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR, the address break function generates an interrupt request to the CPU. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked because of the I bit in CCR of the CPU. Figures 4.
Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A Program 0258 025A * 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked.
Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock divider. The subclock pulse generator consists of a subclock oscillator and a subclock divider. Figure 5.1 shows a block diagram of the clock pulse generators.
Section 5 Clock Pulse Generators 5.1 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system clock generator. OSC 2 LPM OSC 1 LPM: Low-power mode (standby mode, subactive mode, subsleep mode) Figure 5.2 Block Diagram of System Clock Generator 5.1.1 Connecting Crystal Resonator Figure 5.
Section 5 Clock Pulse Generators Table 5.1 Crystal Resonator Parameters Frequency (MHz) 2 4 8 10 16 20 RS (max.) 500 Ω 120 Ω 80 Ω 60 Ω 50 Ω 40 Ω C0 (max.) 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator. C1 OSC1 C2 OSC2 C1 = 5 to 30pF C2 = 5 to 30pF Figure 5.5 Typical Connection to Ceramic Resonator 5.1.
Section 5 Clock Pulse Generators 5.2 Subclock Generator Figure 5.7 shows a block diagram of the subclock generator. X2 8 MΩ X1 Note: Resistance is a reference value. Figure 5.7 Block Diagram of Subclock Generator 5.2.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.8. Figure 5.9 shows the equivalent circuit of the 32.768-kHz crystal resonator. C1 X1 C2 X2 C1 = C 2 = 15 pF (typ.
Section 5 Clock Pulse Generators 5.2.2 Pin Connection when not Using Subclock When the subclock is not used, connect pin X1 to VCL or VSS and leave pin X2 open, as shown in figure 5.10. VCL or VSS X1 X2 Open Figure 5.10 Pin Connection when not Using Subclock 5.3 Prescalers 5.3.1 Prescaler S Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once per clock period.
Section 5 Clock Pulse Generators 5.4 Usage Notes 5.4.1 Notes on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator element manufacturer.
Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has five modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. The module standby function reduces power consumption by selectively halting on-chip module functions. • Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
Section 6 Power-Down Modes 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Bit Bit Name Initial Value R/W Description 7 SSBY 0 R/W Software Standby This bit selects the mode to transit after the execution of the SLEEP instruction. 0: Enters sleep mode or subsleep mode. 1: Enters standby mode. For details, see table 6.2.
Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time Bit Name Operating Frequency STS2 STS1 STS0 Waiting Time 0 0 1 1 0 1 20 MHz 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 0 8,192 states 0.4 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 states 0.8 1.0 1.6 2.0 4.1 8.2 16.4 32.8 0 32,768 states 1.6 2.0 3.3 4.1 8.2 16.4 32.8 65.5 1 65,536 states 3.3 4.1 6.6 8.2 16.4 32.8 65.5 131.1 0 131,072 states 6.6 8.2 13.1 16.4 32.8 65.5 131.
Section 6 Power-Down Modes Bit Bit Name Initial Value R/W Description 1 SA1 0 R/W Subactive Mode Clock Select 1 and 0 0 SA0 0 R/W These bits select the operating clock frequency in subactive and subsleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 00: φW/8 01: φW/4 1x: φW/2 [Legend] x: Don't care. Rev. 3.00 Mar.
Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W Description 7 0 Reserved This bit is always read as 0.
Section 6 Power-Down Modes 6.1.4 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W Description 7 MSTS3_2 0 R/W SCI3_2 Module Standby SCI3_2 enters standby mode when this bit is set to1 6 0 Reserved 5 0 These bits are always read as 0. 4 MSTTB1 0 R/W Timer B1 Module Standby 3 0 Reserved 2 0 These bits are always read as 0.
Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program.
Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode due to Interrupt DTON SSBY SMSEL LSON Transition Mode after SLEEP Instruction Execution 0 0 0 0 Sleep mode 1 1 0 [Legend] * Active mode Subactive mode Subsleep mode 1 1 Transition Mode due to Interrupt Active mode Subactive mode 1 X X Standby mode Active mode X 0* 0 Active mode (direct transition) — X X 1 Subactive mode (direct transition) — X: Don't care.
Section 6 Power-Down Modes Table 6.
Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register.
Section 6 Power-Down Modes 6.2.3 Subsleep Mode In subsleep mode, operation of the CPU and on-chip peripheral modules other than RTC is halted. As long as a required voltage is applied, the contents of CPU registers, the on-chip RAM, and some registers of the on-chip peripheral modules are retained. I/O ports keep the same states as before the transition. Subsleep mode is cleared by an interrupt. When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts.
Section 6 Power-Down Modes 6.3 Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. 6.4 Direct Transition The CPU can execute programs in two modes: active and subactive modes. A direct transition is a transition between these two modes without stopping program execution.
Section 6 Power-Down Modes 6.4.2 Direct Transition from Subactive Mode to Active Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2).
Section 6 Power-Down Modes Rev. 3.00 Mar.
Section 7 ROM Section 7 ROM The features of the 96-kbyte flash memory built into the flash memory (F-ZTAT) version are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 kbyte × 4 blocks, 28 kbytes × 1 block, 16 kbytes × 2 blocks, and 32 kbytes × 1 block for H8/36049F. To erase the entire flash memory, each block must be erased in turn.
Section 7 ROM 7.1 Block Configuration Figure 7.1 shows the block configuration of flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The 96-kbyte flash memory is divided into 1 kbyte × 4 blocks, 28 kbytes × 1 block, 16 kbytes × 2 blocks, and 32 kbytes × 1 block. Erasing is performed in these units. Programming is performed in 128-byte units starting from an address with lower eight bits H'00 or H'80.
Section 7 ROM 7.2 Register Descriptions The flash memory has the following registers. • • • • • Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory power control register (FLPWCR) Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode.
Section 7 ROM Bit Bit Name Initial Value R/W Description 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE=1 and ESU=1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while SWE=1 and PSU=1, the flash memory changes to program mode.
Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7 EB7 0 R/W When this bit is set to 1, 32 kbytes of H'010000 to H'017FFF will be erased. 6 EB6 0 R/W When this bit is set to 1, 16 kbytes of H'00C000 to H'00FFFF will be erased.
Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Section 7 ROM 7.3 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1.
Section 7 ROM 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RxD pin high. The RxD and TxD pins should be pulled up on the board if necessary.
Section 7 ROM Boot Mode Operation Host Operation Processing Contents Communication Contents Transfer of number of bytes of programming control program Flash memory erase Bit rate adjustment Boot mode initiation Item Table 7.2 LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free.
Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 16 to 20 MHz 9,600 bps 8 to 16 MHz 4,800 bps 4 to 16 MHz 2,400 bps 2 to 16 MHz 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program.
Section 7 ROM Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode Rev. 3.00 Mar.
Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing.
Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 — 1 1 1 Remains in erased state Table 7.
Section 7 ROM 7.4.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n←1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 10 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs * n←n+1 Read verify data No Verify data + all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4µs All erase block erased ? n ≤100 ? Yes Yes No Yes SWE bit ← 0 SWE bi
Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode.
Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset. 7.
Section 7 ROM Table 7.7 Flash Memory Operating States Flash Memory Operating State LSI Operating State PDWND = 0 (Initial Value) PDWND = 1 Active mode Normal operating mode Normal operating mode Subactive mode Power-down mode Normal operating mode Sleep mode Normal operating mode Normal operating mode Subsleep mode Standby mode Standby mode Standby mode Standby mode Standby mode Rev. 3.00 Mar.
Section 7 ROM Rev. 3.00 Mar.
Section 8 RAM Section 8 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
Section 8 RAM Rev. 3.00 Mar.
Section 9 I/O Ports Section 9 I/O Ports The group of this LSI has fifty-nine general I/O ports and eight general input-only ports. Thirteen ports are large current ports, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings.
Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W Description 7 IRQ3 0 R/W Selects the function of pin P17/IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6 IRQ2 0 R/W Selects the function of pin P16/IRQ2. 0: General I/O port 1: IRQ2 input pin 5 IRQ1 0 R/W Selects the function of pin P15/IRQ1/TMIB1.
Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W Description 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR14 0 W Bit 3 is a reserved bit.
Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7 PUCR17 0 R/W 6 PUCR16 0 R/W 5 PUCR15 0 R/W Only bits for which PCR1 is cleared are valid. The pullup MOSs of P17 to P14 and P12 to P10 pins enter the on-state when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 4 PUCR14 0 R/W Bit 3 is a reserved bit.
Section 9 I/O Ports • P15/IRQ1/TMIB1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Pin Function Setting value 0 0 P15 input pin 1 P15 output pin X IRQ1 input/TMIB1 input pin 1 [Legend] X: Don't care. • P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Pin Function Setting value 0 0 P14 input pin 1 P14 output pin X IRQ0 input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports • P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Pin Function Setting value 0 0 P10 input pin 1 P10 output pin X TMOW output pin 1 [Legend] 9.2 X: Don't care. Port 2 Port 2 is a general I/O port also functioning as SCI3 I/O pins. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses. P24 P23 Port 2 P22/TXD P21/RXD P20/SCK3 Figure 9.
Section 9 I/O Ports 9.2.1 Port Control Register 2 (PCR2) PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2. Bit Bit Name Initial Value R/W Description 7 Reserved 6 5 4 PCR24 0 W 3 PCR23 0 W 2 PCR22 0 W 1 PCR21 0 W 0 PCR20 0 W 9.2.
Section 9 I/O Ports 9.2.3 Port Mode Register 3 (PMR3) PMR3 selects the CMOS output or NMOS open-drain output for port 2. Bit Bit Name Initial Value R/W Description 7 0 Reserved 6 0 These bits are always read as 0. 5 0 4 POF24 0 R/W 3 POF23 0 R/W When the bit is set to 1, the corresponding pin is cut off by PMOS and it functions as the NMOS open-drain output. When cleared to 0, the pin functions as the CMOS output.
Section 9 I/O Ports • P22/TXD pin Register PMR1 PCR2 Bit Name TXD PCR22 Pin Function Setting Value 0 0 P22 input pin 1 P22 output pin X TXD output pin 1 [Legend] X: Don't care. • P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Pin Function Setting Value 0 0 P21 input pin 1 P21 output pin X RXD input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports 9.3 Port 3 Port 3 is a general I/O port. Each pin of the port 3 is shown in figure 9.3. P37 P36 P35 P34 Port 3 P33 P32 P31 P30 Figure 9.3 Port 3 Pin Configuration Port 3 has the following registers. • Port control register 3 (PCR3) • Port data register 3 (PDR3) 9.3.1 Port Control Register 3 (PCR3) PCR3 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 3.
Section 9 I/O Ports 9.3.2 Port Data Register 3 (PDR3) PDR3 is a general I/O port data register of port 3. Bit Bit Name Initial Value R/W Description 7 P37 0 R/W PDR3 stores output data for port 3 pins. 6 P36 0 R/W 5 P35 0 R/W 4 P34 0 R/W If PDR3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read. If PDR3 is read while PCR3 bits are cleared to 0, the pin states are read regardless of the value stored in PDR3.
Section 9 I/O Ports • P35 pin Register PCR3 Bit Name PCR35 Pin Function Setting Value 0 P35 input pin 1 P35 output pin • P34 pin Register PCR3 Bit Name PCR34 Setting Value 0 1 Pin Function P34 input pin P34 output pin • P33 pin Register PCR3 Bit Name PCR33 Setting Value 0 1 Pin Function P33 input pin P33 output pin • P32 pin Register PCR3 Bit Name PCR32 Setting Value 0 1 Pin Function P32 input pin P32 output pin • P31 pin Register PCR3 Bit Name PCR31 Setting Value 0 1 Pin F
Section 9 I/O Ports • P30 pin Register PCR3 Bit Name PCR30 Setting Value 0 1 9.4 Pin Function P30 input pin P30 output pin Port 5 Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin, an A/D trigger input pin, and a wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.4. The register setting of the I2C bus interface has priority for functions of the pins P57/SCL and P56/SDA.
Section 9 I/O Ports 9.4.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W Description 7 POF57 0 R/W 6 POF56 0 R/W When the bit is set to 1, the corresponding pin is cut off by PMOS and it functions as the NMOS open-drain output. When cleared to 0, the pin functions as the CMOS output. 5 WKP5 0 R/W Selects the function of pin P55/WKP5/ADTRG.
Section 9 I/O Ports 9.4.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Bit Name Initial Value R/W Description 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W When each of the port 5 pins P57 to P50 functions as a general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Section 9 I/O Ports 9.4.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7 0 Reserved 6 0 These bits are always read as 0. 5 PUCR55 0 R/W 4 PUCR54 0 R/W 3 PUCR53 0 R/W Only bits for which PCR5 is cleared are valid.
Section 9 I/O Ports • P56/SDA pin Register ICCR PCR5 Bit Name ICE PCR56 Pin Function Setting Value 0 0 P56 input pin 1 P56 output pin X SDA I/O pin 1 [Legend] X: Don't care. SDA performs the NMOS open-drain output, that enables a direct bus drive. • P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function Setting Value 0 0 P55 input pin 1 P55 output pin X WKP5/ADTRG input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports • P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Pin Function Setting Value 0 0 P52 input pin 1 P52 output pin X WKP2 input pin 1 [Legend] X: Don't care. • P51/WKP1 pin Register PMR5 PCR5 Bit Name WKP1 PCR51 Pin Function Setting Value 0 0 P51 input pin 1 P51 output pin X WKP1 input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports 9.5 Port 6 Port 6 is a general I/O port also functioning as a timer Z I/O pin. Each pin of the port 6 is shown in figure 9.5. The register setting of the timer Z has priority for functions of the pins for both uses. P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 Port 6 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 Figure 9.5 Port 6 Pin Configuration Port 6 has the following registers. • Port control register 6 (PCR6) • Port data register 6 (PDR6) 9.5.
Section 9 I/O Ports 9.5.2 Port Data Register 6 (PDR6) PDR6 is a general I/O port data register of port 6. Bit Bit Name Initial Value R/W Description 7 P67 0 R/W PDR6 stores output data for port 6 pins. 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W If PDR6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read. If PDR6 is read while PCR6 bits are cleared to 0, the pin states are read regardless of the value stored in PDR6.
Section 9 I/O Ports • P66/FTIOC1 pin Register TOER TFCR TPMR TIORC1 PCR6 Bit Name EC1 CMD1, CMD0 PWMC1 IOC2 to IOC0 PCR66 Setting Value 1 00 0 000 or 1XX 0 0 [Legend] 00 0 001 or 01X 1 XXX Other than X 00 XXX Pin Function P66 input/FTIOC1 input pin 1 P66 output pin X FTIOC1 output pin X: Don't care.
Section 9 I/O Ports • P63/FTIOD0 pin Register TOER TFCR TPMR TIORC0 PCR6 Bit Name ED0 CMD1, CMD0 PWMD0 IOD2 to IOD0 PCR63 Pin Function Setting Value 1 00 0 000 or 1XX 0 P63 input/FTIOD0 input pin 1 P63 output pin X FTIOD0 output pin 0 [Legend] 00 0 001 or 01X 1 XXX Other than X 00 XXX X: Don't care.
Section 9 I/O Ports • P61/FTIOB0 pin Register TOER TFCR TPMR TIORA0 PCR6 Bit Name EB0 CMD1, CMD0 PWMB0 IOB2 to IOB0 PCR61 Pin Function Setting Value 1 00 0 000 or 1XX 0 P61 input/FTIOB0 input pin 1 P61 output pin X FTIOB0 output pin 0 [Legend] 00 0 001 or 01X 1 XXX Other than X 00 XXX X: Don't care.
Section 9 I/O Ports 9.6 Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin and SCI3_2 I/O pin. Each pin of the port 7 is shown in figure 9.6. The register settings of the timer V and SCI3_2 have priority for functions of the pins for both uses. P77 P76/TMOV P75/TMCIV Port 7 P74/TMRIV P72/TXD_2 P71/RXD_2 P70/SCK3_2 Figure 9.6 Port 7 Pin Configuration Port 7 has the following registers. • Port control register 7 (PCR7) • Port data register 7 (PDR7) 9.6.
Section 9 I/O Ports 9.6.2 Port Data Register 7 (PDR7) PDR7 is a general I/O port data register of port 7. Bit Bit Name Initial Value R/W Description 7 P77 0 R/W PDR7 stores output data for port 7 pins. 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W If PDR7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read. If PDR7 is read while PCR7 bits are cleared to 0, the pin states are read regardless of the value stored in PDR7. 3 1 Bit 3 is a reserved bit.
Section 9 I/O Ports • P75/TMCIV pin Register PCR7 Bit Name PCR75 Pin Function Setting Value 0 P75 input/TMCIV input pin 1 P75 output/TMCIV input pin • P74/TMRIV pin Register PCR7 Bit Name PCR74 Pin Function Setting Value 0 P74 input/TMRIV input pin 1 P74 output/TMRIV input pin • P72/TXD_2 pin Register PMR1 PCR7 Bit Name TXD2 PCR72 Pin Function Setting Value 0 0 P72 input pin 1 P72 output pin X TXD_2 output pin 1 [Legend] X: Don't care.
Section 9 I/O Ports • P70/SCK3_2 pin Register SCR3_2 SMR_2 PCR7 Bit Name CKE1 CKE0 COM PCR70 Pin Function Setting Value 0 0 0 0 P70 input pin 1 P70 output pin [Legend] 9.7 0 0 1 X SCK3_2 output pin 0 1 X X SCK3_2 output pin 1 X X X SCK3_2 input pin X: Don't care. Port 8 Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.7.
Section 9 I/O Ports 9.7.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8. Bit Bit Name Initial Value R/W Description 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W When each of the port 8 pins P87 to P80 functions as a general I/O port, setting a PCR8 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Section 9 I/O Ports 9.7.3 Pin Functions The correspondence between the register specification and the port functions is shown below.
Section 9 I/O Ports • P83/FTIOC pin Register TMRW Bit Name PWMC IOC2 IOC1 IOC0 PCR83 Pin Function Setting Value 0 0 0 0 0 P83 input/FTIOC input pin 1 P83 output/FTIOC input pin 1 [Legend] X: TIOR1 PCR8 0 0 1 X FTIOC output pin 0 1 X X FTIOC output pin 1 X X X X X 0 P83 input/FTIOC input pin 1 P83 output/FTIOC input pin X PWM output Don't care.
Section 9 I/O Ports • P81/FTIOA pin Register TIOR0 PCR8 Bit Name IOA2 IOA1 IOA0 PCR81 Pin Function Setting Value 0 0 0 0 P81 input/FTIOA input pin 1 P81 output/FTIOA input pin [Legend] 0 0 1 X FTIOA output pin 0 1 X X FTIOA output pin 1 X X 0 P81 input/FTIOA input pin 1 P81 output/FTIOA input pin X: Don't care. • P80/FTCI pin Register PCR8 Bit Name PCR80 Pin Function Setting Value 0 P80 input/FTCI input pin 1 P80 output/FTCI input pin 9.
Section 9 I/O Ports Port 9 has the following registers. • Port control register 9 (PCR9) • Port data register 9 (PDR9) 9.8.1 Port Control Register 9 (PCR9) PCR9 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 9.
Section 9 I/O Ports 9.8.3 Pin Functions The correspondence between the register specification and the port functions is shown below.
Section 9 I/O Ports • P92/TXD_3 pin Register SMCR3 PCR9 Bit Name TXD_3 PCR92 Pin Function Setting Value 0 0 P92 input pin 1 P92 output pin X TXD_3 output pin 1 [Legend] X: Don't care. • P91/RXD_3 pin Register SCR3_3 PCR9 Bit Name RE PCR91 Pin Function Setting Value 0 0 P91 input pin 1 P91 output pin X RXD_3 input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports 9.9 Port B Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.9. PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 Port B PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 9.9 Port B Pin Configuration Port B has the following register. • Port data register B (PDRB) 9.9.1 Port Data Register B (PDRB) PDRB is a general input-only port data register of port B.
Section 9 I/O Ports Rev. 3.00 Mar.
Section 10 Realtime Clock (RTC) Section 10 Realtime Clock (RTC) The realtime clock (RTC) is a timer used to count time ranging from a second to a week. Figure 10.1 shows the block diagram of the RTC. 10.
Section 10 Realtime Clock (RTC) 10.2 Input/Output Pin Table 10.1 shows the RTC input/output pin. Table 10.1 Pin Configuration Name Abbreviation I/O Function Clock output TMOW Output RTC divided clock output 10.3 Register Descriptions The RTC has the following registers.
Section 10 Realtime Clock (RTC) 10.3.1 Second Data Register/Free Running Counter Data Register (RSECDR) RSECDR counts the BCD-coded second value. The setting range is decimal 00 to 59. It is an 8-bit read register used as a counter, when it operates as a free running counter. For more information on reading seconds, minutes, hours, and day-of-week, see section 10.4.3, Data Reading Procedure.
Section 10 Realtime Clock (RTC) 10.3.2 Minute Data Register (RMINDR) RMINDR counts the BCD-coded minute value on the carry generated once per minute by the RSECDR counting. The setting range is decimal 00 to 59. Bit Bit Name Initial Value R/W Description 7 BSY — R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
Section 10 Realtime Clock (RTC) 10.3.3 Hour Data Register (RHRDR) RHRDR counts the BCD-coded hour value on the carry generated once per hour by RMINDR. The setting range is either decimal 00 to 11 or 00 to 23 by the selection of the 12/24 bit in RTCCR1. Bit Bit Name Initial Value R/W Description 7 BSY — R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
Section 10 Realtime Clock (RTC) 10.3.4 Day-of-Week Data Register (RWKDR) RWKDR counts the BCD-coded day-of-week value on the carry generated once per day by RHRDR. The setting range is decimal 0 to 6 using bits WK2 to WK0. Bit Bit Name Initial Value R/W Description 7 BSY — R RTC Busy This bit is set to 1 when the RTC is updating (operating) the values of second, minute, hour, and day-of-week data registers.
Section 10 Realtime Clock (RTC) 10.3.5 RTC Control Register 1 (RTCCR1) RTCCR1 controls start/stop and reset of the clock timer. For the definition of time expression, see figure 10.2. Bit Bit Name Initial Value R/W Description 7 RUN — R/W 6 12/24 — R/W 5 PM — R/W 4 RST 0 R/W 3 INT — R/W RTC Operation Start 0: Stops RTC operation 1: Starts RTC operation Operating Mode 0: RTC operates in 12-hour mode. RHRDR counts on 0 to 11. 1: RTC operates in 24-hour mode.
Section 10 Realtime Clock (RTC) Noon 24-hour count 0 12-hour count 0 PM 1 1 2 2 3 3 4 4 5 6 7 5 6 7 0 (Morning) 8 8 9 10 11 12 13 14 15 16 17 9 10 11 0 1 2 3 4 5 1 (Afternoon) 24-hour count 18 19 20 21 22 23 0 12-hour count 6 7 8 9 10 11 0 1 (Afternoon) 0 PM Figure 10.2 Definition of Time Expression Rev. 3.00 Mar.
Section 10 Realtime Clock (RTC) 10.3.6 RTC Control Register 2 (RTCCR2) RTCCR2 controls RTC periodic interrupts of weeks, days, hours, minutes, and seconds. Enabling interrupts of weeks, days, hours, minutes, and seconds sets the IRRTA flag to 1 in the interrupt flag register 1 (IRR1) when an interrupt occurs. It also controls an overflow interrupt of a free running counter when RTC operates as a free running counter.
Section 10 Realtime Clock (RTC) 10.3.7 Clock Source Select Register (RTCCSR) RTCCSR selects clock source. A free running counter controls start/stop of counter operation by the RUN bit in RTCCR1. When a clock other than 32.768 kHz is selected, the RTC is disabled and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running counter, RSECDR enables counter values to be read.
Section 10 Realtime Clock (RTC) 10.4 Operation 10.4.1 Initial Settings of Registers after Power-On The RTC registers that store second, minute, hour, and day-of week data are not reset by a RES input. Therefore, all registers must be set to their initial values after power-on. Once the register setting are made, the RTC provides an accurate time as long as power is supplied regardless of a RES input. 10.4.2 Initial Setting Procedure Figure 10.3 shows the procedure for the initial setting of the RTC.
Section 10 Realtime Clock (RTC) 10.4.3 Data Reading Procedure When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 10.4 shows an example in which correct data is not obtained. In this example, since only RSECDR is read after data update, about 1-minute inconsistency occurs. To avoid reading in this timing, the following processing must be performed. 1.
Section 10 Realtime Clock (RTC) 10.5 Interrupt Sources There are five kinds of RTC interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts. When using an interrupt, initiate the RTC last after other registers are set. Do not set multiple interrupt enable bits in RTCCR2 simultaneously to 1. When an interrupt request of the RTC occurs, the IRRTA flag in IRR1 is set to 1. When clearing the flag, write 0. Table 10.
Section 10 Realtime Clock (RTC) Rev. 3.00 Mar.
Section 11 Timer B1 Section 11 Timer B1 Timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 11.1 shows a block diagram of timer B1. 11.1 Features • Selection of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/64, φ/16, and φ/4) or an external clock (can be used to count external events). • An interrupt is generated when the counter overflows.
Section 11 Timer B1 11.3 Register Descriptions The timer B1 has the following registers. • Timer mode register B1 (TMB1) • Timer counter B1 (TCB1) • Timer load register B1 (TLB1) 11.3.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock. Bit Bit Name Initial Value R/W Description 7 TMB17 0 R/W Auto-Reload Function Select 0: Interval timer function selected 1: Auto-reload function selected 6 1 Reserved 5 1 These bits are always read as 1.
Section 11 Timer B1 11.3.2 Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. TCB1 is initialized to H'00. 11.3.
Section 11 Timer B1 11.4.2 Auto-Reload Timer Operation Setting bit TMB17 in TMB1 to 1 causes timer B1 to function as an 8-bit auto-reload timer. When a reload value is set in TLB1, the same value is loaded into TCB1, becoming the value from which TCB1 starts its count. After the count value in TCB1 reaches H'FF, the next clock signal input causes timer B1 to overflow. The TLB1 value is then loaded into TCB1, and the count continues from that value.
Section 12 Timer V Section 12 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 12.1 shows a block diagram of timer V. 12.
Section 12 Timer V TCRV1 TCORB Trigger control TMCIV Comparator TCNTV Clock select Internal data bus TRGV Comparator φ PSS TCORA TMRIV Clear control TCRV0 Interrupt request control TMOV Output control [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0 TCSRV TCRV1: PSS: CMIA: CMIB: OVI: Timer control register V1 Prescaler S Compare-match interrupt A Compare-match interrupt B O
Section 12 Timer V 12.2 Input/Output Pins Table 12.1 shows the timer V pin configuration. Table 12.1 Pin Configuration Name Abbreviation I/O Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input External input to reset TCNTV Trigger input TRGV Input Trigger input to initiate counting 12.3 Register Descriptions Time V has the following registers.
Section 12 Timer V 12.3.2 Time Constant Registers A, B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit readable/writable registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle.
Section 12 Timer V 12.3.3 Timer Control Register V0 (TCRV0) TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request. Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 3 CCLR1 CCLR0 0 0 R/W R/W 2 1 0 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Compare Match Interrupt Enable B When this bit is set to 1, interrupt request from the CMFB bit in TCSRV is enabled.
Section 12 Timer V Table 12.
Section 12 Timer V Bit Bit Name Initial Value R/W Description 5 OVF 0 R/W Timer Overflow Flag Setting condition: When TCNTV overflows from H'FF to H'00 Clearing condition: After reading OVF = 1, cleared by writing 0 to OVF 4 1 Reserved This bit is always read as 1. 3 OS3 0 R/W Output Select 3 and 2 2 OS2 0 R/W These bits select an output method for the TOMV pin by the compare match of TCORB and TCNTV.
Section 12 Timer V 12.3.5 Timer Control Register V1 (TCRV1) TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved 4 TVEG1 0 R/W TRGV Input Edge Select 3 TVEG0 0 R/W These bits select the TRGV input edge. These bits are always read as 1.
Section 12 Timer V 12.4 Operation 12.4.1 Timer V Operation 1. According to table 12.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure 12.2 shows the count timing with an internal clock signal selected, and figure 12.3 shows the count timing with both edges of an external clock signal selected. 2.
Section 12 Timer V φ Internal clock TCNTV input clock TCNTV N–1 N N+1 Figure 12.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock TCNTV N–1 N Figure 12.3 Increment Timing with External Clock φ TCNTV H'FF H'00 Overflow signal OVF Figure 12.4 OVF Set Timing Rev. 3.00 Mar.
Section 12 Timer V φ TCNTV N TCORA or TCORB N N+1 Compare match signal CMFA or CMFB Figure 12.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output pin Figure 12.6 TMOV Output Timing φ Compare match A signal TCNTV N H'00 Figure 12.7 Clear Timing by Compare Match Rev. 3.00 Mar.
Section 12 Timer V φ Compare match A signal Timer V output pin N–1 TCNTV N H'00 Figure 12.8 Clear Timing by TMRIV Input 12.5 Timer V Application Examples 12.5.1 Pulse Output with Arbitrary Duty Cycle Figure 12.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2.
Section 12 Timer V 12.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 12.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3.
Section 12 Timer V 12.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. 2. 3. 4. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 12.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence.
Section 12 Timer V TCORA write cycle by CPU T2 T3 T1 φ Address TCORA address Internal write signal TCNTV N TCORA N N+1 M TCORA write data Compare match signal Inhibited Figure 12.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 12.13 Internal Clock Switching and TCNTV Operation Rev. 3.00 Mar.
Section 12 Timer V Rev. 3.00 Mar.
Section 13 Timer W Section 13 Timer W The timer W is a 16-bit timer having output compare and input capture functions. Timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems. 13.
Section 13 Timer W Table 13.1 summarizes the timer W functions, and figure 13.1 shows a block diagram of timer W. Table 13.
Section 13 Timer W Internal clock: φ φ/2 φ/4 φ/8 External clock: FTCI FTIOA Clock selector FTIOB FTIOC Control logic FTIOD Comparator Bus interface [Legend] TMRW: Timer mode register W (8 bits) TCRW: Timer control register W (8 bits) TIERW: Timer interrupt enable register W (8 bits) TSRW: Timer status register W (8 bits) TIOR: Timer I/O control register (8 bits) TCNT: Timer counter (16 bits) GRA: General register A (input capture/output compare register: 16 bits) GRB: General register B (input captu
Section 13 Timer W 13.2 Input/Output Pins Table 13.2 summarizes the timer W pins. Table 13.
Section 13 Timer W 13.3.1 Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Bit Bit Name Initial Value R/W Description 7 CTS 0 R/W Counter Start The counter operation is halted when this bit is 0; while it can be performed when this bit is 1. 6 1 Reserved This bit is always read as 1. 5 BUFEB 0 R/W Buffer Operation B Selects the GRD function.
Section 13 Timer W 13.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer initial output levels. Bit Bit Name Initial Value R/W Description 7 CCLR 0 R/W Counter Clear The TCNT value is cleared by compare match A when this bit is 1. When it is 0, TCNT operates as a freerunning counter. 6 CKS2 0 R/W Clock Select 2 to 0 5 CKS1 0 R/W Select the TCNT clock source.
Section 13 Timer W Bit Bit Name Initial Value R/W Description 0 TOA 0 R/W Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Initial output value is 0* 1: Initial output value is 1* [Legend] x: Don't care. Note: * The change of the setting is immediately reflected in the output value. 13.3.3 Timer Interrupt Enable Register W (TIERW) TIERW controls the timer W interrupt request.
Section 13 Timer W 13.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Bit Bit Name Initial Value R/W Description 7 OVF 0 R/W Timer Overflow Flag [Setting condition] • When TCNT overflows from H'FFFF to H'0000 [Clearing condition] • 6 to 4 All 1 Read OVF when OVF=1, then write 0 in OVF Reserved These bits are always read as 1.
Section 13 Timer W Bit Bit Name Initial Value R/W Description 1 IMFB 0 R/W Input Capture/Compare Match Flag B [Setting conditions] • TCNT=GRB when GRB functions as an output compare register • The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register [Clearing condition] • 0 IMFA 0 R/W Read IMFB when IMFB=1, then write 0 in IMFB Input Capture/Compare Match Flag A [Setting conditions] • TCNT=GRA when GRA functions as an output compare
Section 13 Timer W Bit Bit Name Initial Value R/W Description 5 IOB1 0 R/W I/O Control B1 and B0 4 IOB0 0 R/W When IOB2 = 0, 00: No output at compare match 01: 0 output to the FTIOB pin at GRB compare match 10: 1 output to the FTIOB pin at GRB compare match 11: Output toggles to the FTIOB pin at GRB compare match When IOB2 = 1, 00: Input capture at rising edge at the FTIOB pin 01: Input capture at falling edge at the FTIOB pin 1x: Input capture at rising edge and falling edge at the FTIOB pin
Section 13 Timer W 13.3.6 Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Bit Bit Name Initial Value R/W Description 7 1 6 IOD2 0 R/W 5 4 IOD1 IOD0 0 0 R/W R/W Reserved This bit is always read as 1. I/O Control D2 Selects the GRD function.
Section 13 Timer W Bit Bit Name Initial Value R/W Description 1 0 IOC1 IOC0 0 0 R/W R/W I/O Control C1 and C0 When IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC2 = 1, 00: Input capture to GRC at rising edge of the FTIOC pin 01: Input capture to GRC at falling edge of the FTIOC pin 1x: Input capture to GRC at rising edge and falling edge
Section 13 Timer W 13.3.8 General Registers A to D (GRA to GRD) Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TIOR0 and TIOR1. When a general register is used as an output-compare register, its value is constantly compared with the TCNT value. When the two values match (a compare match), the corresponding flag (IMFA, IMFB, IMFC, or IMFD) in TSRW is set to 1.
Section 13 Timer W 13.4 Operation The timer W has the following operation modes: • Normal Operation • PWM Operation 13.4.1 Normal Operation TCNT performs free-running or periodic counting operations. After a reset, TCNT is set as a freerunning counter. When the CST bit in TMRW is set to 1, TCNT starts incrementing the count. When the count overflows from H'FFFF to H'0000, the OVF flag in TSRW is set to 1. If the OVIE in TIERW is set to 1, an interrupt request is generated. Figure 13.
Section 13 Timer W Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt request is generated. TCNT continues counting from H'0000. Figure 13.3 shows periodic counting. TCNT value GRA H'0000 Time CST bit Flag cleared by software IMFA Figure 13.
Section 13 Timer W Figure 13.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B. TCNT value H'FFFF GRA GRB Time H'0000 FTIOA Toggle output FTIOB Toggle output Figure 13.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 13.6 shows another example of toggle output when TCNT operates as a periodic counter, cleared by compare match A. Toggle output is selected for both compare match A and B.
Section 13 Timer W By setting a general register as an input-capture register, the TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured. Figure 13.
Section 13 Timer W Figure 13.8 shows an example of buffer operation when the GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TCNT operates as a free-running counter, and FTIOA captures both rising and falling edge of the input signal. Due to the buffer operation, the GRA value is transferred to GRC by input-capture A and the TCNT value is stored in GRA.
Section 13 Timer W 13.4.2 PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the cycle register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically. The output level of each pin depends on the corresponding timer output level set bit (TOB, TOC, TOD) in TCRW.
Section 13 Timer W Figure 13.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0). TCNT value Counter cleared by compare match A GRA GRB GRC GRD Time H'0000 FTIOB FTIOC FTIOD Figure 13.10 PWM Mode Example (2) Rev. 3.00 Mar.
Section 13 Timer W Figure 13.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs.
Section 13 Timer W Figures 13.12 and 13.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%. TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 0% FTIOB Output does not change when cycle register and duty register compare matches occur simultaneously. TCNT value Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 100% FTIOB Output does not change when cycle register and duty register compare matches occur simultaneously.
Section 13 Timer W TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 100% FTIOB Output does not change when cycle register and duty register compare matches occur simultaneously. TCNT value Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 0% FTIOB Output does not change when cycle register and duty register compare matches occur simultaneously. TCNT value Write to GRB GRA Write to GRB Write to GRB GRB H'0000 FTIOB Time Duty 0% Duty 100% Figure 13.
Section 13 Timer W 13.5 Operation Timing 13.5.1 TCNT Count Timing Figure 13.14 shows the TCNT count timing when the internal clock source is selected. Figure 13.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted correctly. φ Internal clock Rising edge TCNT input clock TCNT N N+1 N+2 Figure 13.
Section 13 Timer W 13.5.2 Output Compare Timing The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches a general register, the compare match signal is generated only after the next counter clock pulse is input. Figure 13.
Section 13 Timer W 13.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 13.17 shows the timing when the falling edge is selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. φ Input capture input Input capture signal N–1 TCNT N N+1 N+2 N GRA to GRD Figure 13.17 Input Capture Input Signal Timing 13.5.
Section 13 Timer W 13.5.5 Buffer Operation Timing Figures 13.19 and 13.20 show the buffer operation timing. φ Compare match signal TCNT N GRC, GRD M N+1 M GRA, GRB Figure 13.19 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N GRA, GRB M GRC, GRD N+1 N N+1 M N Figure 13.20 Buffer Operation Timing (Input Capture) Rev. 3.00 Mar.
Section 13 Timer W 13.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register. The compare match signal is generated in the last state in which the values match (when TCNT changes from the matching value to the next value).
Section 13 Timer W 13.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 13.22 shows the timing of the IMFA to IMFD flag setting at input capture. φ Input capture signal TCNT N GRA to GRD N IMFA to IMFD IRRTW Figure 13.22 Timing of IMFA to IMFD Flag Setting at Input Capture 13.5.
Section 13 Timer W 13.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. 2. Writing to registers is performed in the T2 state of a TCNT write cycle.
Section 13 Timer W Previous clock New clock Count clock TCNT N N+1 N+2 N+3 The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. Figure 13.25 Internal Clock Switching and TCNT Operation Rev. 3.00 Mar.
Section 13 Timer W 5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the values read from the TOA to TOD bits may differ. Moreover, when the writing to TCRW and the generation of the compare match A to D occur at the same timing, the writing to TCRW has the priority.
Section 14 Timer Z Section 14 Timer Z The timer Z has a 16-bit timer with two channels. Figures 14.1, 14.2, and 14.3 show the block diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z functions, see table 14.1. 14.
Section 14 Timer Z • Eleven interrupt sources Four compare match/input capture interrupts and an overflow interrupt are available for each channel. An underflow interrupt can be set for channel 1. Table 14.
Section 14 Timer Z ITMZ0 FTIOA0 FTIOB0 FTIOC0 FTIOD0 ITMZ1 Control logic FTIOA1 FTIOB1 FTIOC1 FTIOD1 φ, φ/2, φ/4, φ/8 ADTRG TSTR TMDR Channel 0 timer Channel 1 timer TPMR TFCR TOER TOCR Module data bus [Legend] TSTR: TMDR: TPMR: TFCR: TOER: TOCR: ADTRG: ITMZ0: ITMZ1: Timer start register (8 bits) Timer mode register (8 bits) Timer PWM mode register (8 bits) Timer function control register (8 bits) Timer output master enable register (8 bits) Timer output control register (8 bits) A/D conversion s
Section 14 Timer Z FTIOA0 φ, φ/2, φ/4, φ/8 FTIOB0 FTIOC0 FTIOD0 Clock select Control logic ITMZ0 POCR_0 TIER_0 TSR_0 TIORC_0 TIORA_0 TCR_0 GRD_0 GRC_0 GRB_0 GRA_0 TCNT_0 Comparator Module data bus [Legend] TCNT_0 GRA_0, GRB_0: : GRC_0, GRD_0 TCR_0: : TIORA_0: TIORC_0: TSR_0: TIER_0: POCR_0: ITMZ0: Timer counter_0 (16 bits) General registers A_0, B_0, C_0, and D_0 (input capture/output compare registers: 16 bits × 4) Timer control register_0 (8 bits) Timer I/O control register A_0 (8 bits)
Section 14 Timer Z FTIOA1 φ, φ/2, φ/4, φ/8 FTIOB1 FTIOC1 FTIOD1 Clock select Control logic ITMZ1 POCR_1 TIER_1 TSR_1 TIORC_1 TIORA_1 TCR_1 GRD_1 GRC_1 GRB_1 GRA_1 TCNT_1 Comparator Module data bus [Legend] TCNT_1: GRA_1, GRB_1: GRC_1, GRD_1: TCR_1: TIORA_1: TIORC_1: TSR_1: TIER_1: POCR_1: ITMZ1: Timer counter_1 (16 bits) General registers A_1, B_1, C_1, and D_1 (input capture/output compare registers: 16 bits × 4) Timer control register_1 (8 bits) Timer I/O control register A_1 (8 bits) Ti
Section 14 Timer Z 14.2 Input/Output Pins Table 14.2 summarizes the timer Z pins. Table 14.
Section 14 Timer Z 14.3 Register Descriptions The timer Z has the following registers.
Section 14 Timer Z • General register C_1 (GRC_1) • General register D_1 (GRD_1) 14.3.1 Timer Start Register (TSTR) TSTR selects the operation/stop for the TCNT counter. Bit Bit Name Initial Value R/W Description 7 to 2 All 1 Reserved These bits are always read as 1, and cannot be modified. 1 STR1 0 R/W Channel 1 Counter Start 0: TCNT_1 halts counting 1: TCNT_1 starts counting 0 STR0 0 R/W Channel 0 Counter Start 0: TCNT_0 halts counting 1: TCNT_0 starts counting Rev. 3.00 Mar.
Section 14 Timer Z 14.3.2 Timer Mode Register (TMDR) TMDR selects buffer operation settings and synchronized operation.
Section 14 Timer Z 14.3.3 Timer PWM Mode Register (TPMR) TPMR sets the pin to enter PWM mode. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1, and cannot be modified.
Section 14 Timer Z 14.3.4 Timer Function Control Register (TFCR) TFCR selects the settings and output levels for each operating mode. Bit Bit Name Initial Value R/W 7 1 Description Reserved This bit is always read as 1.
Section 14 Timer Z Bit Bit Name Initial Value R/W Description 1 CMD1 0 R/W Combination Mode 1 and 0 0 CMD0 0 R/W 00: Channel 0 and channel 1 operate normally 01: Channel 0 and channel 1 are used together to operate in reset synchronous PWM mode 10: Channel 0 and channel 1 are used together to operate in complementary PWM mode (transferred at the trough) 11: Channel 0 and channel 1 are used together to operate in complementary PWM mode (transferred at the crest) Note: When reset synchronous PW
Section 14 Timer Z 14.3.5 Timer Output Master Enable Register (TOER) TOER enables/disables the outputs for channel 0 and channel 1. When WKP4 is selected for inputs, if a low level signal is input to WKP4, the bits in TOER are set to 1 to disable the output for timer Z.
Section 14 Timer Z Bit Bit Name Initial Value R/W Description 2 EC0 1 R/W Master Enable C0 0: FTIOC0 pin output is enabled according to the TPMR, TFCR, and TIORC_0 settings 1: FTIOC0 pin output is disabled regardless of the TPMR, TFCR, and TIORC_0 settings (FTIOC0 pin is operated as an I/O port).
Section 14 Timer Z 14.3.6 Timer Output Control Register (TOCR) TOCR selects the initial outputs before the first occurrence of a compare match. Note that bits OLS1 and OLS0 in TFCR set these initial outputs in reset synchronous PWM mode and complementary PWM mode.
Section 14 Timer Z 14.3.7 Timer Counter (TCNT) The timer Z has two TCNT counters (TCNT_0 and TCNT_1), one for each channel. The TCNT counters are 16-bit readable/writable registers that increment/decrement according to input clocks. Input clocks can be selected by bits TPSC2 to TPSC0 in TCR. TCNT0 and TCNT 1 increment/decrement in complementary PWM mode, while they only increment in other modes.
Section 14 Timer Z 14.3.9 Timer Control Register (TCR) The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Section 14 Timer Z 14.3.10 Timer I/O Control Register (TIORA and TIORC) The TIOR registers control the general registers (GR). Timer Z has four TIOR registers (TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid. TIORA: TIORA selects whether GRA or GRB is used as an output compare register or an input capture register.
Section 14 Timer Z TIORC: TIORC selects whether GRC or GRD is used as an output compare register or an input capture register. When an output compare register is selected, the output setting is selected. When an input capture register is selected, an input edge of an input capture signal is selected. TIORC also selects the function of FTIOC or FTIOD pin. Bit Bit Name Initial Value R/W 7 1 Description Reserved This bit is always read as 1.
Section 14 Timer Z 14.3.11 Timer Status Register (TSR) TSR indicates generation of an overflow/underflow of TCNT and a compare match/input capture of GRA, GRB, GRC, and GRD. These flags are interrupt sources. If an interrupt is enabled by a corresponding bit in TIER, TSR requests an interrupt for the CPU. Timer Z has two TSR registers, one for each channel. Bit Bit Name Initial Value R/W Description 7, 6 All 1 Reserved These bits are always read as 1.
Section 14 Timer Z Bit Bit Name Initial Value R/W Description 2 IMFC 0 R/W Input Capture/Compare Match Flag C [Setting conditions] • When TCNT = GRC and GRC is functioning as output compare register • When TCNT value is transferred to GRC by input capture signal and GRC is functioning as input capture register [Clearing condition] • 1 IMFB 0 R/W When 0 is written to IMFC after reading IMFC = 1 Input Capture/Compare Match Flag B [Setting conditions] • When TCNT = GRB and GRB is functionin
Section 14 Timer Z 14.3.12 Timer Interrupt Enable Register (TIER) TIER enables or disables interrupt requests for overflow or GR compare match/input capture. Timer Z has two TIER registers, one for each channel. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved 4 OVIE 0 R/W Overflow Interrupt Enable These bits are always read as 1.
Section 14 Timer Z 14.3.13 PWM Mode Output Level Control Register (POCR) POCR control the active level in PWM mode. Timer Z has two POCR registers, one for each channel. Bit Bit Name Initial Value R/W Description 7 to 3 All 1 Reserved 2 POLD 0 R/W PWM Mode Output Level Control D These bits are always read as 1.
Section 14 Timer Z 14.3.14 Interface with CPU 1. 16-bit register TCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be accessed in a 16-bit unit. Figure 14.5 shows an example of accessing the 16-bit registers. Internal data bus H C P L Module data bus Bus interface U TCNTH TCNTL Figure 14.5 Accessing Operation of 16-Bit Register (between CPU and TCNT (16 bits)) 2.
Section 14 Timer Z 14.4 Operation 14.4.1 Counter Operation When one of bits STR0 and STR1 in TSTR is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. Figure 14.7 shows an example of the counter operation setting procedure.
Section 14 Timer Z 1. Free-running count operation and periodic count operation Immediately after a reset, the TCNT counters for channels 0 and 1 are all designated as freerunning counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter starts an increment operation as a free-running counter. When TCNT overflows, the OVF flag in TSR is set to 1. If the value of the OVIE bit in the corresponding TIER is 1 at this point, timer Z requests an interrupt.
Section 14 Timer Z Figure 14.9 illustrates periodic counter operation. TCNT value Counter cleared by GR compare match GR value H'0000 Time STR IMF Figure 14.9 Periodic Counter Operation 2. TCNT count timing A. Internal clock operation A system clock (φ) or three types of clocks (φ/2, φ/4, or φ/8) that divides the system clock can be selected by bits TPSC2 to TPSC0 in TCR. Figure 14.10 illustrates this timing. φ Internal clock TCNT input TCNT N-1 N+1 N Figure 14.
Section 14 Timer Z B. External clock operation An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TCR, and a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the rising edge, falling edge, or both edges can be selected. The pulse width of the external clock needs two or more system clocks. Note that an external clock does not operate correctly with the lower pulse width. Figure 14.
Section 14 Timer Z 14.4.2 Waveform Output by Compare Match Timer Z can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or FTIOD output pin using compare match A, B, C, or D. Figure 14.12 shows an example of the setting procedure for waveform output by compare match.
Section 14 Timer Z 1. Examples of waveform output operation Figure 14.13 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made such that 0 is output by compare match A, and 1 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF Time H'0000 FTIOB No change No change FTIOA No change No change Figure 14.
Section 14 Timer Z TCNT value GRB GRA Time H'0000 FTIOB Toggle output FTIOA Toggle output Figure 14.14 Example of Toggle Output Operation 2. Output compare timing The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD).
Section 14 Timer Z 14.4.3 Input Capture Function The TCNT value can be transferred to GR on detection of the input edge of the input capture/output compare pin (FTIOA, FTIOB, FTIOC, or FTIOD). Rising edge, falling edge, or both edges can be selected as the detected edge. When the input capture function is used, the pulse width or period can be measured. Figure 14.16 shows an example of the input capture operation setting procedure.
Section 14 Timer Z 1. Example of input capture operation Figure 14.17 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the FTIOA pin input capture input edge, the falling edge has been selected as the FTIOB pin input capture input edge, and counter clearing by GRB input capture has been designated for TCNT.
Section 14 Timer Z 2. Input capture signal timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR. Figure 14.18 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles. φ Input capture input Input capture signal TCNT N GR N Figure 14.18 Input Capture Signal Timing Rev. 3.00 Mar.
Section 14 Timer Z 14.4.4 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables GR to be increased with respect to a single time base. Figure 14.19 shows an example of the synchronous operation setting procedure.
Section 14 Timer Z Figure 14.20 shows an example of synchronous operation. In this example, synchronous operation has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. In addition, the same input clock has been set as the counter input clock for channel 0 and channel 1. Two-phase PWM waveforms are output from pins FTIOB0 and FTIOB1.
Section 14 Timer Z Figure 14.21 shows an example of the PWM mode setting procedure. Table 14.3 Initial Output Level of FTIOB0 Pin TOB0 POLB Initial Output Level 0 0 1 0 1 0 1 0 0 1 1 1 PWM mode [1] [1] Select counter clock [2] Select counter clearing source Set PWM mode [2] [3] [3] [4] Set initial output level [4] [5] Select output level [5] [6] Set GR [6] [7] [8] Enable waveform output [7] Start counter operation Select the counter clock with bits TPSC2 to TOSC0 in TCR.
Section 14 Timer Z Figure 14.22 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is reset at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0). TCNT value Counter cleared by GRA compare match GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 14.22 Example of PWM Mode Operation (1) Rev. 3.00 Mar.
Section 14 Timer Z Figure 14.23 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is reset at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1). TCNT value Counter cleared by GRA compare match GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 14.23 Example of PWM Mode Operation (2) Figures 14.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 14.
Section 14 Timer Z TCNT value GRB rewritten GRA GRB GRB rewritten Time H'0000 0% duty FTIOB TCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRA GRB rewritten GRB rewritten GRB H'0000 Time FTIOB 100% duty When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
Section 14 Timer Z TCNT value GRB rewritten GRA GRB rewritten GRB H'0000 Time FTIOB 0% duty TCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRA GRB rewritten GRB rewritten GRB Time H'0000 100% duty FTIOB TCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
Section 14 Timer Z 14.4.6 Reset Synchronous PWM Mode Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 performs an increment operation. Tables 14.4 and 14.5 show the PWM-output pins used and the register settings, respectively. Figure 14.
Section 14 Timer Z Reset synchronous PWM mode Stop counter operation [1] Select counter clock [2] Select counter clearing source [3] Set reset synchronous PWM mode [4] Initialize the output pin [5] Set TCNT [6] Set GR [7] Enable waveform output [8] Start counter operation [9] [1] [2] [3] [4] [5] [6] [7] [8] [9] Clear bit STR0 in TSTR to 0 and stop the counter operation of TCNT_0. Set reset synchronous PWM mode after TCNT_0 stops.
Section 14 Timer Z Figures 14.27 and 14.28 show examples of operation in reset synchronous PWM mode. TCNT value Counter cleared by GRA compare match GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 14.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) Rev. 3.00 Mar.
Section 14 Timer Z TCNT value Counter cleared by GRA compare match GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 14.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) In reset synchronous PWM mode, TCNT_0 and TCNT_1 perform increment and independent operations, respectively. However, GRA_1 and GRB_1 are separated from TCNT_1.
Section 14 Timer Z 14.4.7 Complementary PWM Mode Three PWM waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 and TCNT_1 perform an increment or decrement operation. Tables 14.6 and 14.7 show the output pins and register settings in complementary PWM mode, respectively. Figure 14.
Section 14 Timer Z [1] Complementary PWM mode Stop counter operation [1] [2] [3] Initialize output pin [2] Select counter clock [3] Set complementary PWM mode [4] Initialize output pin [5] Set TCNT [6] [4] [5] [6] [7] [7] Set GR Enable waveform output [8] Start counter operation [9] [8] [9] Note: Clear bits STR0 and STR1 in TSTR to 0, and stop the counter operation of TCNT_0. Stop TCNT_0 and TCNT_1 and set complementary PWM mode. Write H'00 to TOCR.
Section 14 Timer Z 1. Canceling Procedure of Complementary PWM Mode: Figure 14.30 shows the complementary PWM mode canceling procedure. Complementary PWM mode [1] Stop counter operation [1] [2] Cancel complementary PWM mode [2] Clear bit CMD1 in TFCR to 0, and set channels 0 and 1 to normal operation. After setting channels 0 and 1 to normal operation, clear bits STR0 and STR1 in TSTR to 0 and stop TCNT0 and TCNT1. Figure 14.30 Canceling Procedure of Complementary PWM Mode Rev.
Section 14 Timer Z 2. Examples of Complementary PWM Mode Operation: Figure 14.31 shows an example of complementary PWM mode operation. In complementary PWM mode, TCNT_0 and TCNT_1 perform an increment or decrement operation. When TCNT_0 and GRA_0 are compared and their contents match, the counter is decremented, and when TCNT_1 underflows, the counter is incremented.
Section 14 Timer Z Figure 14.32 (1) and (2) show examples of PWM waveform output with 0% duty and 100% duty in complementary PWM mode (for one phase). • TPSC2 = TPSC1 = TPSC0 = 0 Set GRB_0 to H'0000 or a value equal to or more than GRA_0. The waveform with a duty cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation. For details on buffer operation, see section 14.4.8, Buffer Operation.
Section 14 Timer Z TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 0% duty (a) When duty is 0% TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 100% duty (b) When duty is 100% Figure 14.32 (1) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 = 0) (2) Rev. 3.00 Mar.
Section 14 Timer Z TCNT values GRA0 GRB0 H'0000 Time FTIOB0 0% duty FTIOD0 (a) When duty is 0% TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 100% duty (b) When duty is 100% Figure 14.32 (2) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 ≠ 0) (3) Rev. 3.00 Mar.
Section 14 Timer Z In complementary PWM mode, when the counter switches from up-counter to down-counter or vice versa, TCNT_0 and TCNT_1 overshoots or undershoots, respectively. In this case, the conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings are shown in figures 14.33 and 14.34.
Section 14 Timer Z When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been designated for BR, BR is transferred to GR when the counter is incremented by compare match A0 or when TCNT_1 is underflowed. If the φ or φ/2 clock is selected by TPSC2 to TPSC0 bits, the OVF flag is not set to 1 at the timing that the counter value changes from H'FFFF to H'0000.
Section 14 Timer Z • To output a 100%-duty cycle waveform, write H'0000 while previous GR value< TCNT_0 ≤ GRA_0 • • b. • • c. • • To change duty cycles while a waveform with a duty cycle of 0% or 100% is being output, make sure the following procedure.
Section 14 Timer Z d. Buffer operation is used and other than TPSC2 = TPSC1 = TPSC0 = 0 Write a value which satisfies GRA_0 + 1 < GR < H'FFFF to the buffer register. A waveform with a duty cycle of 0% can be output. However, a waveform with a duty cycle of 100% cannot be output using the buffer operation. Also, the buffer operation cannot be used to change duty cycles while a waveform with a duty cycle of 100% is being output. For details on buffer operation, see section 14.4.8, Buffer Operation. 14.4.
Section 14 Timer Z 2. When GR is an input capture register When an input capture occurs, the value in TCNT is transferred to the general register and the value previously stored in the general register is transferred to the buffer register. This operation is illustrated in figure 14.36. Input capture signal General register Buffer register TCNT Figure 14.36 Input Capture Buffer Operation 3.
Section 14 Timer Z 6. Examples of Buffer Operation Figure 14.38 shows an operation example in which GRA has been designated as an output compare register, and buffer operation has been designated for GRA and GRC. This is an example of TCNT operating as a periodic counter cleared by compare match B. Pins FTIOA and FTIOB are set for toggle output by compare match A and B.
Section 14 Timer Z φ TCNT n n+1 Compare match signal Buffer transfer signal GRC GRA N n N Figure 14.39 Example of Compare Match Timing for Buffer Operation Figure 14.40 shows an operation example in which GRA has been designated as an input capture register, and buffer operation has been designated for GRA and GRC. Counter clearing by input capture B has been set for TCNT, and falling edges have been selected as the FIOCB pin input capture input edge.
Section 14 Timer Z TCNT value Counter is cleared by the input capture B H'0180 H'0160 H'0005 H'0000 Time FTIOB FTIOA GRA H'0005 H'0160 GRC H'0005 GRB H'0160 H'0180 Input capture A Figure 14.40 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register) Rev. 3.00 Mar.
Section 14 Timer Z φ FTIO pin Input capture signal n+1 TCNT n N N+1 GRA M n n N GRC m M M n Figure 14.41 Input Capture Timing of Buffer Operation Rev. 3.00 Mar.
Section 14 Timer Z Figures 14.42 and 14.43 show the operation examples when buffer operation has been designated for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM waveform of 0% duty is created by using the buffer operation and performing GRD_0 ≥ GRA_0. Data is transferred from GRD_0 to GRB_0 according to the settings of CMD_0 and CMD_1 when TCNT_0 and GRA_0 are compared and their contents match or when TCNT_1 underflows.
Section 14 Timer Z GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values) TCNT values TCNT_0 GRA_0 TCNT_1 H'0999 H'0000 Time GRB_0 GRD_0 H'0999 GRB_0 H'0999 H'0000 H'0999 H'0000 H'0999 FTIOC0 FTIOD0 Figure 14.43 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) Rev. 3.00 Mar.
Section 14 Timer Z 14.4.9 Timer Z Output Timing The outputs of channels 0 and 1 can be disabled or inverted by the settings of TOER and TOCR and the external level. 1. Output Disable/Enable Timing of Timer Z by TOER: Setting the master enable bit in TOER to 1 disables the output of timer Z. By setting the PCR and PDR of the corresponding I/O port beforehand, any value can be output. Figure 14.44 shows the timing to enable or disable the output of timer Z by TOER.
Section 14 Timer Z 2. Output Disable Timing of Timer Z by External Trigger: When P54/WKP4 is set as a WKP4 input pin, and low level is input to WKP4, the master enable bit in TOER is set to 1 and the output of timer Z will be disabled. φ WKP4 TOER N Timer Z output pin H'FF I/O port Timer Z output Timer Z output I/O port Figure 14.45 Example of Output Disable Timing of Timer Z by External Trigger 3.
Section 14 Timer Z 4. Output Inverse Timing by POCR: The output level can be inverted by inverting the POLD, POLC, and POLB bits in POCR in PWM mode. Figure 14.47 shows the timing. T1 T2 φ Address bus POCR address TFCR Timer Z output pin Inverted Figure 14.47 Example of Output Inverse Timing of Timer Z by Writing to POCR 14.5 Interrupts There are three kinds of timer Z interrupt sources; input capture/compare match, overflow, and underflow.
Section 14 Timer Z φ TCNT input clock N TCNT N+1 N GR Compare match signal IMF ITMZ Figure 14.48 IMF Flag Set Timing when Compare Match Occurs 2. IMF Flag Set Timing at Input Capture: When an input capture signal is generated, the IMF flag is set to 1 and the value of TCNT is simultaneously transferred to corresponding GR. Figure 14.49 shows the timing. φ Input capture signal IMF TCNT GR N N ITMZ Figure 14.49 IMF Flag Set Timing at Input Capture Rev. 3.00 Mar.
Section 14 Timer Z 3. Overflow Flag (OVF) Set Timing: The overflow flag is set to 1 when the TCNT overflows. Figure 14.50 shows the timing. φ TCNT H'FFFF H'0000 Overflow signal OVF ITMZ Figure 14.50 OVF Flag Set Timing 14.5.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 14.51 shows the timing in this case. φ Address TSR address WTSR (internal write signal) IMF, OVF ITMZ Figure 14.51 Status Flag Clearing Timing Rev. 3.00 Mar.
Section 14 Timer Z 14.6 Usage Notes 1. Contention between TCNT Write and Clear Operations: If a counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not performed. Figure 14.52 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) Counter clear signal N TCNT H'0000 Clearing has priority. Figure 14.52 Contention between TCNT Write and Clear Operations 2.
Section 14 Timer Z 3. Contention between GR Write and Compare Match: If a compare match occurs in the T2 state of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure 14.54 shows the timing in this case. GR write cycle T1 T2 φ GR address WGR (internal write signal) TCNT N N+1 GR N M GR write data Compare match signal Disabled Figure 14.54 Contention between GR Write and Compare Match Rev. 3.00 Mar.
Section 14 Timer Z 4. Contention between TCNT Write and Overflow/Underflow: If overflow/underflow occurs in the T2 state of a TCNT write cycle, TCNT write has priority without an increment operation. At this time, the OVF flag is set to 1. Figure 14.55 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) TCNT input clock Overflow signal TCNT H'FFFF M TCNT write data OVF Figure 14.55 Contention between TCNT Write and Overflow Rev. 3.00 Mar.
Section 14 Timer Z 5. Contention between GR Read and Input Capture: If an input capture signal is generated in the T1 state of a GR read cycle, the data that is read will be transferred before input capture transfer. Figure 14.56 shows the timing in this case. GR read cycle T1 T2 φ GR address Internal read signal Input capture signal M X GR Internal data bus X Figure 14.56 Contention between GR Read and Input Capture Rev. 3.00 Mar.
Section 14 Timer Z 6. Contention between Count Clearing and Increment Operations by Input Capture: If an input capture and increment signals are simultaneously generated, count clearing by the input capture operation has priority without an increment operation. The TCNT contents before clearing counter are transferred to GR. Figure 14.57 shows the timing in this case. φ Input capture signal Counter clear signal TCNT input clock TCNT GR N H'0000 N Clearing has priority. Figure 14.
Section 14 Timer Z 7. Contention between GR Write and Input Capture: If an input capture signal is generated in the T2 state of a GR write cycle, the input capture operation has priority and the write to GR is not performed. Figure 14.58 shows the timing in this case. GR write cycle T1 T2 φ Address bus GR address WGR (internal write signal) Input capture signal TCNT N GR M GR write data Figure 14.58 Contention between GR Write and Input Capture 8.
Section 14 Timer Z TOCR, read the port 6 state to reflect the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 output, to TOA0 to TOD0 and TOA1 to TOD1, and then restart the counter. Figure 14.59 shows an example when the compare match and the bit manipulation instruction to TOCR occur at the same timing. TOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B0.
Section 14 Timer Z Rev. 3.00 Mar.
Section 15 Watchdog Timer Section 15 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 15.1.
Section 15 Watchdog Timer 15.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 15.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction.
Section 15 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 WDON 0 R/W Watchdog Timer On TCWD starts counting up when WDON is set to 1 and halts when WDON is cleared to 0.
Section 15 Watchdog Timer 15.2.2 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00. 15.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit Bit Name Initial Value R/W Description 7 to 4 All 1 Reserved These bits are always read as 1.
Section 15 Watchdog Timer 15.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 256 φosc clock cycles.
Section 15 Watchdog Timer Rev. 3.00 Mar.
Section 16 14-Bit PWM Section 16 14-Bit PWM The 14-bit PWM is a pulse division type PWM that can be used for electronic tuner control, etc. Figure 16.1 shows a block diagram of the 14-bit PWM. 16.
Section 16 14-Bit PWM 16.3 Register Descriptions The 14-bit PWM has the following registers. • PWM control register (PWCR) • PWM data register U (PWDRU) • PWM data register L (PWDRL) 16.3.1 PWM Control Register (PWCR) PWCR selects the conversion period. Bit Bit Name Initial Value R/W Description 7 6 5 4 3 2 1 0 PWCR0 1 1 1 1 1 1 1 0 R/W Reserved These bits are always read as 1, and cannot be modified. [Legend] tφ: Period of PWM clock input Rev. 3.00 Mar.
Section 16 14-Bit PWM 16.3.2 PWM Data Registers U, L (PWDRU, PWDRL) PWDRU and PWDRL indicate high level width in one PWM waveform cycle. PWDRU and PWDRL are 14-bit write-only registers, with the upper 6 bits assigned to PWDRU and the lower 8 bits to PWDRL. When read, all bits are always read as 1. Both PWDRU and PWDRL are accessible only in bytes. Note that the operation is not guaranteed if word access is performed.
Section 16 14-Bit PWM Conversion period t f1 t H1 t f2 t H2 t f63 t H3 t H63 t f64 t H64 T H = t H1 + t H2 + t H3 + ... + t H64 t f1 = t f2 = t f3 = ... = t f64 Figure 16.2 Waveform Output by 14-Bit PWM Rev. 3.00 Mar.
Section 17 Serial Communication Interface 3 (SCI3) Section 17 Serial Communication Interface 3 (SCI3) This LSI includes a serial communication interface 3 (SCI3), which has independent three channels. The SCI3 can handle both asynchronous and clocked synchronous serial communication.
Section 17 Serial Communication Interface 3 (SCI3) Clocked synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors Table 17.
Section 17 Serial Communication Interface 3 (SCI3) Note: 1. In addition to basic functions common to SCI3 and SCI3_2, SCI3_3 has the serial mode control register (SMCR). SMCR controls taking noise from the RXD_3 input signal, P92/TxD_3 pin function, and SCI3_3 module standby function. 2. The channel 1 of the SCI3 is used in on-board programming mode by boot mode.
Section 17 Serial Communication Interface 3 (SCI3) Sampling clock RXD_3 input signal D C D Q Latch C Q Latch D C Q Latch Match detector SCMR3 (NFEF_3) Internal RXD_3 signal in figure 17.
Section 17 Serial Communication Interface 3 (SCI3) 17.2 Input/Output Pins Table 17.2 shows the SCI3 pin configuration. Table 17.2 Pin Configuration Pin Name Abbreviation I/O Function SCI3 clock SCK3 I/O SCI3 clock input/output SCI3 receive data input RXD Input SCI3 receive data input SCI3 transmit data output TXD Output SCI3 transmit data output 17.3 Register Descriptions The SCI3 has the following registers for each channel.
Section 17 Serial Communication Interface 3 (SCI3) 17.3.3 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI3 first transfers transmit data from TDR to TSR automatically, then sends the data that starts from the LSB to the TXD pin. TSR cannot be directly accessed by the CPU. 17.3.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for transmission.
Section 17 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 STOP 0 R/W Stop Bit Length (enabled only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits For reception, only the first stop bit is checked, regardless of the value in the bit. If the second stop bit is 0, it is treated as the start bit of the next transmit character.
Section 17 Serial Communication Interface 3 (SCI3) 17.3.6 Serial Control Register 3 (SCR3) SCR3 is a register that enables or disables SCI3 transfer operations and interrupt requests, and is also used to select the transfer clock source. For details on interrupt requests, see section 17.7, Interrupt Requests. Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When this bit is set to 1, the TXI interrupt request is enabled.
Section 17 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 1 CKE1 0 R/W Clock Enable 0 and 1 0 CKE0 0 R/W Selects the clock source. • Asynchronous mode 00: On-chip baud rate generator 01: On-chip baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK3 pin. 10: External clock Inputs a clock with a frequency 16 times the bit rate from the SCK3 pin.
Section 17 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 6 RDRF 0 R/W Receive Data Register Full Indicates that the received data is stored in RDR.
Section 17 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 1 MPBR 0 R Multiprocessor Bit Receive MPBR stores the multiprocessor bit in the receive character data. When the RE bit in SCR3 is cleared to 0, its state is retained. 0 MPBT 0 R/W Multiprocessor Bit Transfer MPBT stores the multiprocessor bit to be added to the transmit character data. 17.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate.
Section 17 Serial Communication Interface 3 (SCI3) Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 2 2.097152 2.4576 3 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.
Section 17 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 3.6864 4 4.9152 5 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.
Section 17 Serial Communication Interface 3 (SCI3) Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6 6.144 7.3728 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 150 2 77 0.16 2 79 0.00 2 95 0.00 300 1 155 0.16 1 159 0.00 1 191 0.00 600 1 77 0.16 1 79 0.00 1 95 0.00 1200 0 155 0.16 0 159 0.00 0 191 0.00 2400 0 77 0.16 0 79 0.
Section 17 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 8 9.8304 10 12 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03 150 2 103 0.16 2 127 0.00 2 129 0.16 2 155 0.16 300 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 600 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16 1200 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16 2400 0 103 0.
Section 17 Serial Communication Interface 3 (SCI3) Table 17.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ (MHz) 12.888 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.16 2 191 0.00 2 207 0.16 300 2 79 0.00 2 90 0.16 2 95 0.00 2 103 0.16 600 1 159 0.00 1 181 0.16 1 191 0.00 1 207 0.
Section 17 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 18 20 Bit Rate (bit/s) n N Error (%) n N Error (%) 110 3 79 –0.12 3 88 –0.25 150 2 233 0.16 3 64 0.16 300 2 116 0.16 2 129 0.16 600 1 233 0.16 2 64 0.16 1200 1 116 0.16 1 129 0.16 2400 0 233 0.16 1 64 0.16 4800 0 116 0.16 0 129 0.16 9600 0 58 –0.96 0 64 0.16 19200 0 28 1.02 0 32 –1.36 31250 0 17 0.00 0 19 0.00 38400 0 14 –2.34 0 15 1.
Section 17 Serial Communication Interface 3 (SCI3) Table 17.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) Operating Frequency φ (MHz) Bit Rate (bit/s) 110 250 500 1k 2.
Section 17 Serial Communication Interface 3 (SCI3) Table 17.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) Operating Frequency φ (MHz) 18 20 Bit Rate (bit/s) n N n N 110 — — — — 250 — — — — 500 3 140 3 155 1k 3 69 3 77 2.5k 2 112 2 124 5k 1 224 1 249 10k 1 112 1 124 25k 0 179 0 199 50k 0 89 0 99 100k 0 44 0 49 250k 0 17 0 19 500k 0 8 0 9 1M 0 4 0 4 2M — — — — 2.
Section 17 Serial Communication Interface 3 (SCI3) 17.4 Operation in Asynchronous Mode Figure 17.2 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex.
Section 17 Serial Communication Interface 3 (SCI3) 17.4.2 SCI3 Initialization Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize the SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Section 17 Serial Communication Interface 3 (SCI3) 17.4.3 Data Transmission Figure 17.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission.
Section 17 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0.
Section 17 Serial Communication Interface 3 (SCI3) 17.4.4 Serial Data Reception Figure 17.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 17 Serial Communication Interface 3 (SCI3) Table 17.6 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 17.8 shows a sample flow chart for serial data reception. Table 17.
Section 17 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 No [4] [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically.
Section 17 Serial Communication Interface 3 (SCI3) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 17.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2) Rev. 3.00 Mar.
Section 17 Serial Communication Interface 3 (SCI3) 17.5 Operation in Clocked Synchronous Mode Figure 17.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next.
Section 17 Serial Communication Interface 3 (SCI3) 17.5.3 Serial Data Transmission Figure 17.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission.
Section 17 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. [2] To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
Section 17 Serial Communication Interface 3 (SCI3) 17.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 17.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. 2. 3. 4. The SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. The SCI3 stores the receive data in RSR.
Section 17 Serial Communication Interface 3 (SCI3) Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 17.13 shows a sample flow chart for serial data reception. Start reception [1] Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. [2] Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR.
Section 17 Serial Communication Interface 3 (SCI3) 17.5.5 Simultaneous Serial Data Transmission and Reception Figure 17.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Section 17 Serial Communication Interface 3 (SCI3) 17.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Section 17 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving station A (ID = 01) Serial data Receiving station B (ID = 02) H'01 Receiving station C (ID = 03) Receiving station D (ID = 04) H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 17.
Section 17 Serial Communication Interface 3 (SCI3) 17.6.1 Multiprocessor Serial Data Transmission Figure 17.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same as those in asynchronous mode.
Section 17 Serial Communication Interface 3 (SCI3) 17.6.2 Multiprocessor Serial Data Reception Figure 17.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 17.
Section 17 Serial Communication Interface 3 (SCI3) [5] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No [A] Framing error processing Clear OER, and FER flags in SSR to 0 Figure 17.17 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 3.00 Mar.
Section 17 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation User processing RXI interrupt request is not generated, and RDR retains its state RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 RDR data read When data is not this station's ID, MPIE is set to 1 again (a)
Section 17 Serial Communication Interface 3 (SCI3) 17.7 Interrupt Requests SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 17.7 shows the interrupt sources. Table 17.
Section 17 Serial Communication Interface 3 (SCI3) 17.8 Usage Notes 17.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 17.8.
Section 17 Serial Communication Interface 3 (SCI3) 17.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 17.19.
2 Section 18 I C Bus Interface 2 (IIC2) Section 18 I2C Bus Interface 2 (IIC2) The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 18.1 shows a block diagram of the I2C bus interface 2. Figure 18.2 shows an example of I/O pin connections to external circuits. 18.
2 Section 18 I C Bus Interface 2 (IIC2) Transfer clock generation circuit SCL Transmission/ reception control circuit Output control ICCR1 ICCR2 ICMR Internal data bus Noise canceler ICDRT SDA Output control ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICIER [Legend] ICCR1: I2C bus control register 1 ICCR2: I2C bus control register 2 ICMR: I2C bus mode register ICSR: I2C bus status register ICIER: I2C bus interrupt enable reg
2 Section 18 I C Bus Interface 2 (IIC2) Vcc SCL in Vcc SCL SCL SDA SDA SDA in SCL SDA SDA out SCL in (Master) SCL SDA SCL out SCL in SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 18.2 External Circuit Connections of I/O Pins 18.2 Input/Output Pins Table 18.1 summarizes the input/output pins used by the I2C bus interface 2. Table 18.
2 Section 18 I C Bus Interface 2 (IIC2) 18.3 Register Descriptions The I2C bus interface 2 has the following registers. • • • • • • • • • I2C bus control register 1 (ICCR1) I2C bus control register 2 (ICCR2) I2C bus mode register (ICMR) I2C bus interrupt enable register (ICIER) I2C bus status register (ICSR) I2C bus slave address register (SAR) I2C bus transmit data register (ICDRT) I2C bus receive data register (ICDRR) I2C bus shift register (ICDRS) 18.3.
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 5 4 MST TRS 0 0 R/W R/W 3 2 1 0 CKS3 CKS2 CKS1 CKS0 0 0 0 0 R/W R/W R/W R/W Master/Slave Select Transmit/Receive Select 2 In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames.
2 Section 18 I C Bus Interface 2 (IIC2) Table 18.2 Transfer Rate Bit 3 Bit 2 Bit 1 Bit 0 CKS3 CKS2 CKS1 CKS0 Clock φ=5 MHz 0 0 0 0 φ/28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz 1 φ/40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz 0 φ/48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz 1 φ/64 78.1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 0 φ/80 62.5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 φ/100 50.0 kHz 80.0 kHz 100 kHz 160 kHz 200 kHz 0 φ/112 44.6 kHz 71.4 kHz 89.
2 Section 18 I C Bus Interface 2 (IIC2) 18.3.2 I2C Bus Control Register 2 (ICCR2) ICCR2 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial 2 format, this bit has no meaning.
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 SDAOP 1 R/W SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. 3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low.
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 6 WAIT 0 R/W 5 4 1 Wait Insertion Bit In master mode with the I2C bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted.
2 Section 18 I C Bus Interface 2 (IIC2) 18.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled.
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NAKIE 0 R/W NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt request (NAKI) and the overrun error (setting of the OVE bit in ICSR) interrupt request (ERI) with the clocked synchronous format, when the NACKF and AL bits in ICSR are set to 1. NAKI can be canceled by clearing the NACKF, OVE, or NAKIE bit to 0. 0: NACK receive interrupt request (NAKI) is disabled.
2 Section 18 I C Bus Interface 2 (IIC2) 18.3.5 I2C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status.
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] • 3 STOP 0 R/W When 0 is written in NACKF after reading NACKF = 1 Stop Condition Detection Flag [Setting conditions] • In master mode, when a stop condition is detected after frame transfer • In slave mode, when a st
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 2 AL/OVE 0 R/W Arbitration Lost Flag/Overrun Error Flag This flag indicates that arbitration was lost in master 2 mode with the I C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format.
2 Section 18 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 0 ADZ 0 R/W General Call Address Recognition Flag 2 This bit is valid in I C bus format slave receive mode. [Setting condition] • When the general call address is detected in slave receive mode [Clearing condition] • 18.3.6 When 0 is written in ADZ after reading ADZ=1 Slave Address Register (SAR) SAR selects the communication format and sets the slave address.
2 Section 18 I C Bus Interface 2 (IIC2) 18.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.
2 Section 18 I C Bus Interface 2 (IIC2) 18.4 Operation The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 18.4.1 I2C Bus Format Figure 18.3 shows the I2C bus formats. Figure 18.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
2 Section 18 I C Bus Interface 2 (IIC2) [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. 18.4.
2 Section 18 I C Bus Interface 2 (IIC2) SCL (Master output) 1 2 3 4 5 6 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 9 1 Bit 0 Slave address Bit 7 2 Bit 6 R/W SDA (Slave output) A TDRE TEND Address + R/W ICDRT ICDRS Data 1 Address + R/W User [2] Instruction of start processing condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) [3] Write data to ICDRT (first byte) Figure 18.
2 Section 18 I C Bus Interface 2 (IIC2) 18.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, see figures 18.7 and 18.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode.
2 Section 18 I C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 9 SDA (Master output) SDA (Slave output) 1 A A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 18.7 Master Receive Mode Operation Timing (1) Rev. 3.00 Mar.
2 Section 18 I C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) A SDA (Slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n Data n-1 ICDRR User processing Data n Data n-1 [5] Read ICDRR after setting RCVD [7] Read ICDRR, and clear RCVD [6] Issue stop condition [8] Set slave receive mode Figure 18.8 Master Receive Mode Operation Timing (2) 18.4.
2 Section 18 I C Bus Interface 2 (IIC2) Slave receive mode SCL (Master output) Slave transmit mode 9 1 2 3 4 5 6 7 8 SDA (Master output) 9 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS ICDRT ICDRS Data 1 Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 18.
2 Section 18 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 18.10 Slave Transmit Mode Operation Timing (2) 18.4.
2 Section 18 I C Bus Interface 2 (IIC2) 4. The last byte data is read by reading ICDRR. SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 1 Bit 7 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 1 Data 2 ICDRR User processing Data 1 [2] Read ICDRR [2] Read ICDRR (dummy read) Figure 18.
2 Section 18 I C Bus Interface 2 (IIC2) 18.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. Data Transfer Format Figure 18.13 shows the clocked synchronous serial transfer format.
2 Section 18 I C Bus Interface 2 (IIC2) SCL 1 2 7 8 1 7 8 1 SDA (Output) Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 TRS TDRE Data 1 ICDRT Data 1 ICDRS User processing Data 2 [3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS Data 3 Data 2 Data 3 [3] Write data to ICDRT [3] Write data to ICDRT Figure 18.14 Transmit Mode Operation Timing Receive Operation In receive mode, data is latched at the rise of the transfer clock.
2 Section 18 I C Bus Interface 2 (IIC2) SCL 1 2 7 8 1 7 8 SDA (Input) Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 1 2 Bit 0 MST TRS RDRF Data 2 Data 1 ICDRS Data 3 Data 1 ICDRR User processing [2] Set MST (when outputting the clock) [3] Read ICDRR Data 2 [3] Read ICDRR Figure 18.15 Receive Mode Operation Timing 18.4.7 Noise Canceller The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched internally. Figure 18.
2 Section 18 I C Bus Interface 2 (IIC2) 18.4.8 Example of Use Flowcharts in respective modes that use the I2C bus interface are shown in figures 18.17 to 18.20. Start Initialize Read BBSY in ICCR2 No [2] Set master transmit mode. [3] Issue the start candition. Yes Set MST and TRS in ICCR1 to 1. [2] [4] Set the first byte (slave address + R/W) of transmit data. Write 1 to BBSY and 0 to SCP. [3] [5] Wait for 1 byte to be transmitted.
2 Section 18 I C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* Clear TEND in ICSR Clear TRS in ICCR1 to 0 [1] [3] Dummy-read ICDDR.* Clear TDRE in ICSR Clear ACKBT in ICIER to 0 Dummy-read ICDRR Read RDRF in ICSR No RDRF=1 ? [2] [4] Wait for 1 byte to be received [3] [5] Check whether it is the (last receive - 1). [6] Read the receive data last. [4] [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
2 Section 18 I C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. [5] Wait for the last byte to be transmitted. Read TDRE in ICSR No [3] [6] Clear the TEND flag . TDRE=1 ? [7] Set slave receive mode. Yes No [2] Set transmit data for ICDRT (except for the last data). [8] Dummy-read ICDRR to release the SCL line. Last byte? Yes [4] [9] Clear the TDRE flag.
2 Section 18 I C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [4] Wait for 1 byte to be received. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? No Read ICDRR Yes [8] Read the (last byte - 1) of receive data.
2 Section 18 I C Bus Interface 2 (IIC2) 18.5 Interrupts There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun error. Table 18.3 shows the contents of each interrupt request. Table 18.
2 Section 18 I C Bus Interface 2 (IIC2) 18.6 Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 18.21 shows the timing of the bit synchronous circuit and table 18.
2 Section 18 I C Bus Interface 2 (IIC2) 18.7 Usage Notes 18.7.1 Issue (Retransmission) of Start/Stop Conditions In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. To avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check the SCLO bit in the I2C control register 2 (IICR2) to confirm the fall of the ninth clock. 1.
2 Section 18 I C Bus Interface 2 (IIC2) Rev. 3.00 Mar.
Section 19 A/D Converter Section 19 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 19.1. 19.1 • • • • • • • • Features 10-bit resolution Eight input channels Conversion time: at least 3.
Section 19 A/D Converter Module data bus 10-bit D/A Bus interface Successive approximations register AVCC Internal data bus A D D R A A D D R B A D D R C A D D R D A D C S R A D C R AN1 AN2 AN3 AN4 AN5 AN6 AN7 Analog multiplexer AN0 + φ/4 Control circuit Comparator Sample-andhold circuit ADTRG [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 19.
Section 19 A/D Converter 19.2 Input/Output Pins Table 19.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the analog block in the A/D converter. Table 19.
Section 19 A/D Converter 19.3 Register Descriptions The A/D converter has the following registers. • • • • • • A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion.
Section 19 A/D Converter 19.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Section 19 A/D Converter Bit Bit Name Initial Value R/W Description 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W Select analog input channels. 0 CH0 0 R/W When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4 100: AN4 101: AN5 101: AN4 and AN5 110: AN6 110: AN4 to AN6 111: AN7 111: AN4 to AN7 19.3.
Section 19 A/D Converter Bit Bit Name Initial Value R/W Description 7 TRGE 0 R/W Trigger Enable A/D conversion is started at the falling edge and the rising edge of the external trigger signal (ADTRG) when this bit is set to 1. The selection between the falling edge and rising edge of the external trigger pin (ADTRG) conforms to the WPEG5 bit in the interrupt edge select register 2 (IEGR2) 6 to 4 — All 1 — Reserved These bits are always read as 1.
Section 19 A/D Converter 19.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 19.4.
Section 19 A/D Converter 19.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 19.2 shows the A/D conversion timing. Table 19.3 shows the A/D conversion time. As indicated in figure 19.2, the A/D conversion time includes tD and the input sampling time.
Section 19 A/D Converter Table 19.3 A/D Conversion Time (Single Mode) CKS = 0 Item Symbol Min. A/D conversion start delay time tD Input sampling time tSPL A/D conversion time tCONV CKS = 1 Typ. Max. Min. Typ. Max. 6 — 9 — 31 — 4 — 5 — 15 — 131 — 134 69 — 70 Note: All values represent the number of states. 19.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
Section 19 A/D Converter 19.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 19.4). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 19.5).
Section 19 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 Quantization error 010 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 8 FS Analog input voltage Figure 19.4 A/D Conversion Accuracy Definitions (1) Rev. 3.00 Mar.
Section 19 A/D Converter Digital output Full-scale error Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 19.4 A/D Conversion Accuracy Definitions (2) Rev. 3.00 Mar.
Section 19 A/D Converter 19.6 Usage Notes 19.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) This LSI can include a power-on reset circuit and low-voltage detection circuit as optional circuits. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits.
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) φ CK R OVF PSS R RES Internal reset signal Q Noise canceler S CRES Power-on reset circuit Noise canceler Vcc Ladder resistor Internal data bus LVDCR Vreset + − Vint LVDRES + − LVDINT Interrupt control circuit LVDSR Reference voltage generator Interrupt request Low-voltage detection circuit [Legend] PSS: LVDCR: LVDSR: LVDRES: LVDINT: Vreset: Vint: Prescaler S Low-voltage-detection control register Low-voltage-de
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) 20.2 Register Descriptions The low-voltage detection circuit has the following registers. • Low-voltage-detection control register (LVDCR) • Low-voltage-detection status register (LVDSR) 20.2.
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) Bit Bit Name Initial Value R/W Description 1 LVDDE 0 R/W Voltage-Fall-Interrupt Enable 0: Interrupt on the power-supply voltage falling below the selected detection level disabled 1: Interrupt on the power-supply voltage falling below the selected detection level enabled 0 LVDUE 0 R/W Voltage-Rise-Interrupt Enable 0: Interrupt on the power-supply voltage rising above the selected detection level disabled 1: Interrupt on t
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) 20.2.2 Low-Voltage-Detection Status Register (LVDSR) LVDSR indicates whether the power-supply voltage falls below or rises above the respective specified values. Bit Bit Name Initial Value R/W Description 7 to 2 All 1 Reserved These bits are always read as 1, and cannot be modified. 1 LVDDF 0* R/W LVD Power-Supply Voltage Fall Flag [Setting condition] When the power-supply voltage falls below Vint (D) (typ. = 3.
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) 20.3 Operation 20.3.1 Power-On Reset Circuit Figure 20.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ. 150 kΩ). Since the state of the RES pin is transmitted within the chip, the prescaler S and the entire chip are in their reset states.
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) 20.3.2 Low-Voltage Detection Circuit Use this circuit in the system in which the power supply voltage Vcc is between 4.5 and 5.5 V. If so, the contents described in the section of electrical characteristics are guaranteed. LVDR (Reset by Low Voltage Detect) Circuit: Figure 20.3 shows the timing of the LVDR function. The LVDR enters the module-standby state after a power-on reset is canceled.
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) VCC Vreset VLVDRmin VSS LVDRES PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 20.3 Operational Timing of LVDR Circuit LVDI (Interrupt by Low Voltage Detect) Circuit: Figure 20.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled.
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function is performed. Vint (U) Vint (D) Vcc Vreset1 VSS LVDINT LVDDE LVDDF LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated Figure 20.4 Operational Timing of LVDI Circuit Procedures for Clearing Settings when Using LVDR and LVDI: To operate or release the low-voltage detection circuit normally, follow the procedure described below.
Section 20 Power-On Reset and Low-Voltage Detection Circuits (Optional) LVDE LVDRE LVDDE LVDUE tLVDON Figure 20.5 Timing for Operation/Release of Low-Voltage Detection Circuit Rev. 3.00 Mar.
Section 21 Power Supply Circuit Section 21 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V.
Section 21 Power Supply Circuit 21.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and VCC pin, as shown in figure 21.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
Section 22 List of Registers Section 22 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) • Registers are listed from the lower allocation addresses. • The symbol in the register-name column represents a reserved address or range of reserved addresses. Do not attempt to access reserved addresses.
Section 22 List of Registers 22.1 Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the specified basic clock that is required for access to the register. Note: Access to undefined or reserved addresses is prohibited. Correct operation of the access itself or later operations is not guaranteed when such a register is accessed. Bit No.
Section 22 List of Registers Bit No.
Section 22 List of Registers Bit No.
Section 22 List of Registers Bit No.
Section 22 List of Registers Bit No.
Section 22 List of Registers Data Bus Width Access State Address break 8 2 H'FFFFC9 Address break 8 2 8 H'FFFFCA Address break 8 2 BARL 8 H'FFFFCB Address break 8 2 Break data register H BDRH 8 H'FFFFCC Address break 8 2 Break data register L BDRL 8 H'FFFFCD Address break 8 2 — — — H'FFFFCE — — — Break address register E BARE 8 H'FFFFCF Address break 8 2 Port pull-up control register 1 PUCR1 8 H'FFFFD0 I/O port 8 2 Port pull-up control register 5 PUCR
Section 22 List of Registers Bit No.
Section 22 List of Registers 22.2 Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row.
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name TSR_1 — — UDF OVF IMFD IMFC IMFB IMFA Timer Z1 TIER_1 — — — OVIE IMIED IMIEC IMIEB IMIEA POCR_1 — — — — — POLD POLC POLB TCNT_1 TCNT1H7 TCNT1H6 TCNT1H5 TCNT1H4 TCNT1H3 TCNT1H2 TCNT1H1 TCNT1H0 TCNT1L7 TCNT1L6 TCNT1L5 TCNT1L4 TCNT1L3 TCNT1L2 TCNT1L1 TCNT1L0 GRA_1 GRA1H7 GRA1H6 GRA1H5 GRA1H4 GRA1H3 GRA1H2 GRA1H1 GRA1H0 GRA1L7 GRA1L6 GRA1L5 GRA1L4
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SMR_2 COM CHR PE PM STOP MP CKS1 CKS0 SCI3_2 BRR_2 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 SCR3_2 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDR_2 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 SSR_2 TDRE RDRF OER FER PER TEND MPBR MPBT RDR_2 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 ICCR1 ICE RCVD MST TRS CKS3 CKS2 CKS1 CKS0 ICCR2 BBSY SCP SDAO
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name GRD GRD15 GRD14 GRD13 GRD12 GRD11 GRD10 GRD9 GRD8 Timer W GRD7 GRD6 GRD5 GRD4 GRD3 GRD2 GRD1 GRD0 FLMCR1 — SWE ESU PSU EV PV E P FLMCR2 FLER — — — — — — — FLPWCR PDWND — — — — — — — EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 FENR FLSHE — — — — — — — TCRV0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TCSRV CMFB CFMA OVF — OS3
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PWDRL PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0 14-bit PWM PWDRU — — PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWCR — — — — — — — PWCR0 TCSRWD B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST TCWD TCWD7 TCWD6 TCWD5 TCWD4 TCWD3 TCWD2 TCWD1 TCWD0 TMWD — — — — CKS3 CKS2 CKS1 CKS0 ABRKCR RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1
Section 22 List of Registers Register Module Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name PCR6 PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 I/O port PCR7 PCR77 PCR76 PCR75 PCR74 — PCR72 PCR71 PCR70 PCR8 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 PCR9 PCR97 PCR96 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90 SYSCR1 SSBY STS2 STS1 STS0 NESEL — — — SYSCR2 SMSEL LSON DTON MA2 MA1 MA0 SA1 SA0 IEGR1 NMIEG — — — IEG3 IEG2 IEG1 I
Section 22 List of Registers 22.
Section 22 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module TSTR Initialized — — — — — TMDR Initialized — — — — — Timer Z common TPMR Initialized — — — — — TFCR Initialized — — — — — TOER Initialized — — — — — TOCR Initialized — — — — — RSECDR Initialized — — — — — RMINDR Initialized — — — — — RHRDR Initialized — — — — — RWKDR — — — — — — RTCCR1 — — — — — — RTCCR2 — — — — — — RTCCS
Section 22 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module TMRW Initialized — — — — — Timer W TCRW Initialized — — — — — TIERW Initialized — — — — — TSRW Initialized — — — — — TIOR0 Initialized — — — — — TIOR1 Initialized — — — — — TCNT Initialized — — — — — GRA Initialized — — — — — GRB Initialized — — — — — GRC Initialized — — — — — GRD Initialized — — — — — FLMCR1 Initialized — —
Section 22 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module ADDRD Initialized — — Initialized Initialized Initialized A/D converter ADCSR Initialized — — Initialized Initialized Initialized ADCR Initialized — — Initialized Initialized Initialized PWDRL Initialized — — — — — PWDRU Initialized — — — — — PWCR Initialized — — — — — TCSRWD Initialized — — — — — TCWD Initialized — — — — — TMWD Initialized — — — —
Section 22 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module PCR2 Initialized — — — — — I/O port PCR3 Initialized — — — — — PCR5 Initialized — — — — — PCR6 Initialized — — — — — PCR7 Initialized — — — — — PCR8 Initialized — — — — — PCR9 Initialized — — — — — SYSCR1 Initialized — — — — — SYSCR2 Initialized — — — — — IEGR1 Initialized — — — — — IEGR2 Initialized — — — — — IENR1 Initialized
Section 22 List of Registers Rev. 3.00 Mar.
Section 23 Electrical Characteristics Section 23 Electrical Characteristics 23.1 Absolute Maximum Ratings Table 23.1 Absolute Maximum Ratings Item Symbol Value Unit Notes Power supply voltage VCC –0.3 to +7.0 V * Analog power supply voltage AVCC –0.3 to +7.0 V Input voltage VIN –0.3 to VCC +0.3 V Port B –0.3 to AVCC +0.3 V X1 –0.3 to 4.
Section 23 Electrical Characteristics Power Supply Voltage and Operating Frequency Range φ (MHz) 20.0 φSUB (kHz) 16.384 10.0 8.192 4.096 1.0 φ (kHz) 3.0 4.0 5.5 VCC (V) • AVCC = 3.0 to 5.5 V • Active mode • Sleep mode (When MA2 in SYSCR2 = 0 ) 3.0 4.0 5.5 • AVCC = 3.0 to 5.5 V • Subactive mode • Subsleep mode 2500 1250 78.125 3.0 4.0 5.5 VCC (V) • AVCC = 3.0 to 5.
Section 23 Electrical Characteristics Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used φosc (MHz) 20.0 16.0 2.0 Vcc(V) 3.0 4.5 5.5 Operation guarantee range Operation guarantee range except A/D conversion accuracy Rev. 3.00 Mar.
Section 23 Electrical Characteristics 23.2.2 DC Characteristics Table 23.2 DC Characteristics (1) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Input high VIH voltage Applicable Pins Test Condition RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, SCK3, SCK3_2, SCK3_3, TRGV, FTCI, TMIB1 Typ. Max. Unit VCC = 4.0 to 5.5 V VCC × 0.8 VCC + 0.3 V VCC × 0.9 VCC + 0.3 VCC = 4.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Input low voltage VIL RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TMRIV, VCC = 4.0 to 5.5 V –0.3 VCC × 0.2 V –0.3 VCC × 0.1 –0.3 VCC × 0.3 –0.3 VCC × 0.2 TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, SCK3, SCK3_2, SCK3_3, TRGV, FTCI, TMIB1 RXD, RXD_2, RXD_3, SCL, SDA, P10 to P12, P14 to P17, P20 to P24, P30 to P37, VCC = 4.0 to 5.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Output high voltage VOH P10 to P12, P14 to P17, P20 to P24, P30 to P37, VCC = 4.0 to 5.5 V VCC – 1.0 V P50 to P55, P60 to P67, P70 to P72, P74 to P77, P80 to P87, P90 to P97 –IOH = 0.1 mA VCC – 0.5 P56, P57 4.0 V ≤ VCC ≤ 5.5 V VCC – 2.5 –IOH = 0.1 mA 3.0 V ≤ VCC < 4.0 V VCC – 2.0 –IOH = 0.1 mA Output low voltage VOL –IOH = 1.
Section 23 Electrical Characteristics Values Item Pull-up MOS current Symbol Applicable Pins | IIL | –Ip Min. Typ. Max. Unit OSC1, RES, NMI, VIN = 0.5 V or WKP0 to WKP5, higher (VCC – 0.5 V) IRQ0 to IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, RXD, SCK3, RXD_2, SCK3_2, RXD_3, SCK3_3, SCL, SDA, TMIB1, FTCI 1.0 µA P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67, P70 to P72, P74 to P77, P80 to P87, P90 to P97 VIN = 0.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes Active mode supply current IOPE1 Active mode 1 VCC = 5.0 V, fOSC = 20 MHz 25.0 36.0 mA * Active mode 1 VCC = 3.0 V, fOSC = 10 MHz 11.0 Active mode 2 VCC = 5.0 V, fOSC = 20 MHz 2.3 3.6 Active mode 2 VCC = 3.0 V, fOSC = 10 MHz 1.3 Sleep mode 1 VCC = 5.0 V, fOSC = 20 MHz 18.0 23.0 Sleep mode 1 VCC = 3.0 V, fOSC = 10 MHz 8.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes Standby mode supply current ISTBY VCC 32-kHz crystal resonator not used 5.0 µA * RAM data retaining voltage VRAM VCC 2.0 V Note: Pin states during supply current measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Section 23 Electrical Characteristics Table 23.2 DC Characteristics (2) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Applicable Item Symbol Pins Test Condition Allowable output low current (per pin) IOL Output pins except port 6, P80 to P84, SCL, and SDA Allowable output low current (total) ∑IOL Allowable output high current (per pin) –IOH Allowable output high current (total) –∑IOH Typ. Max. Unit VCC = 4.0 to 5.5 V 2.
Section 23 Electrical Characteristics 23.2.3 AC Characteristics Table 23.3 AC Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Applicable Item Symbol Pins System clock fOSC oscillation frequency System clock (φ) cycle time OSC1, OSC2 Reference Test Condition Min. Typ. Max. Unit Figure VCC = 4.0 to 5.5 V 2.0 20.0 MHz * 2.0 10.0 1 64 tOSC * 12.8 µs tcyc Subclock oscillation fW frequency X1, X2 32.
Section 23 Electrical Characteristics Values Applicable Item Symbol Pins Test Condition RES pin low width tREL RES Min. Reference Typ. Max. Unit Figure At power-on and in trc modes other than those below ms Figure 23.
Section 23 Electrical Characteristics Table 23.4 I2C Bus Interface Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol SCL input cycle time tSCL SCL input high width tSCLH SCL input low width Test Condition Values Min. Typ. Max.
Section 23 Electrical Characteristics Table 23.5 Serial Communication Interface (SCI) Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Applicable Item Symbol Input Asynchro- tScyc clockcycle nous Pins Test Condition SCK3 Clocked synchronous Input clock pulse width tSCKW SCK3 Transmit data delay time (clocked synchronous) tTXD TXD Receive data setup time (clocked synchronous) tRXS Receive data hold time (clocked synchronous) tRXH RXD RXD Rev.
Section 23 Electrical Characteristics 23.2.4 A/D Converter Characteristics Table 23.6 A/D Converter Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol Applicable Pins Test Condition Values Min. Typ. Max. Unit Notes V * Analog power supply AVCC voltage AVCC 3.0 VCC 5.5 Analog input voltage AN0 to AN7 VSS – 0.3 AVCC + 0.3 V 2.0 mA 50 µA AVIN Analog power supply AIOPE current AISTOP1 AVCC AVCC = 5.
Section 23 Electrical Characteristics Item Symbol Applicable Pins Conversion time (single mode) Test Condition Values Min. AVCC = 4.0 to 134 5.5 V Typ. Max. Unit tcyc Nonlinearity error ±3.5 LSB Offset error ±3.5 LSB Full-scale error ±3.5 LSB Quantization error ±0.5 LSB Absolute accuracy ±4.0 LSB Notes Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
Section 23 Electrical Characteristics 23.2.6 Flash Memory Characteristics Table 23.8 Flash Memory Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Test Item Symbol Min. Typ. Max.
Section 23 Electrical Characteristics Values Test Item Erasing Symbol Condition Min. Typ. Max.
Section 23 Electrical Characteristics 23.2.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) Table 23.9 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Test Condition Power-supply falling detection voltage Vint (D) LVDSEL = 0 3.3 3.7 V Power-supply rising detection voltage Vint (U) LVDSEL = 0 4.0 4.5 V Reset detection voltage 1*1 Vreset1 LVDSEL = 0 2.3 2.
Section 23 Electrical Characteristics 23.2.8 Power-On Reset Circuit Characteristics (Optional) Table 23.10 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol Pull-up resistance of RES pin RRES Power-on reset start voltage* Vpor Note: * Values Test Condition Min. 100 Typ. Max.
Section 23 Electrical Characteristics Power Supply Voltage and Operating Frequency Range φ (MHz) 20.0 φSUB (kHz) 16.384 10.0 8.192 4.096 1.0 φ (kHz) 2.7 4.0 5.5 VCC (V) • AVCC = 2.7 to 5.5 V • Active mode • Sleep mode (When MA2 in SYSCR2 = 0) 2.7 4.0 5.5 • AVCC = 2.7 to 5.5 V • Subactive mode • Subsleep mode VCC (V) 2500 1250 78.125 2.7 4.0 5.5 VCC (V) • AVCC = 2.7 to 5.
Section 23 Electrical Characteristics Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used φosc (MHz) 20.0 16.0 2.0 Vcc(V) 3.0 4.5 5.5 Operation guarantee range Operation guarantee range except A/D conversion accuracy Rev. 3.00 Mar.
Section 23 Electrical Characteristics 23.3.2 DC Characteristics Table 23.11 DC Characteristics (1) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Input high voltage VIH RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, SCK3, SCK3_2, SCK3_3, TRGV, FTCI, TMIB1 Typ. Max. Unit VCC = 4.0 to 5.5 V VCC × 0.8 VCC + 0.3 V VCC × 0.9 VCC + 0.3 VCC = 4.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Input low voltage VIL RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, SCK3, SCK3_2, SCK3_3, TRGV, FTCI, TMIB1 RXD, RXD_2, RXD_3, SCL, SDA, P10 to P12, P14 to P17, P20 to P24, P30 to P37, P50 to P57, P60 to P67,. P70 to P72, P74 to P77, P80 to P87, P90 to P97 PB0 to PB7 OSC1 Rev. 3.00 Mar. 15, 2006 Page 446 of 526 REJ09B0060-0300 Min. Typ. Max.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Output high voltage VOH P10 to P12, P14 to P17, P20 to P24, P30 to P37, VCC = 4.0 to 5.5 V VCC – 1.0 V P50 to P55, P60 to P67, P70 to P72, P74 to P76, P80 to P87, P90 to P97 –IOH = 0.1 mA VCC – 0.5 P56, P57 4.0 V ≤ VCC ≤ 5.5 V –IOH = 0.1 mA VCC – 2.5 2.0 V ≤ VCC < 4.0 V –IOH = 0.1 mA VCC – 2.0 P10 to P12, P14 to P17, P20 to P24, P30 to P37, VCC = 4.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Input/ output leakage current | IIL | Pull-up MOS current –Ip RRES Pull-up MOS resistance Input capacitance Cin Test Condition Min. Typ. Max. Unit OSC1, RES, NMI, VIN = 0.5 V or WKP0 to WKP5, higher (VCC – 0.5 V) IRQ0 to IRQ3, ADTRG, TRGV, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, FTIOA to FTIOD, RXD, SCK3, RXD_2, SCK3_2, RXD_3, SCK3_3, SCL, SDA, TMIB1, FTCI 1.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes Active mode supply current IOPE1 VCC Active mode 1 VCC = 5.0 V, fOSC = 20 MHz 25.0 36.0 mA * Active mode 1 VCC = 3.0 V, fOSC = 10 MHz 11.0 Active mode 2 VCC = 5.0 V, fOSC = 20 MHz 2.3 3.6 Active mode 2 VCC = 3.0 V, fOSC = 10 MHz 1.3 Sleep mode 1 VCC = 5.0 V, fOSC = 20 MHz 18.0 23.0 Sleep mode 1 VCC = 3.0 V, fOSC = 10 MHz 8.
Section 23 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Standby mode supply current ISTBY VCC RAM data retaining voltage VRAM VCC Note: Pin states during supply current measurement are given below (excluding current in the pull-up MOS transistors and output buffers). * Min. 32-kHz crystal resonator not used 2.0 Typ. Max. Unit 5.
Section 23 Electrical Characteristics Table 23.11 DC Characteristics (2) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Applicable Item Symbol Pins Test Condition Min. Typ. Max. Unit Allowable output low current (per pin) IOL Output pins except port 6, P80 to P84, SCL, and SDA VCC = 4.0 to 5.5 V 2.0 mA Port 6, P80 to P84 20.0 Output pins except port 6, P80 to P84, SCL, and SDA 0.5 Port 6, P80 to P84 10.0 SCL, SDA 6.
Section 23 Electrical Characteristics 23.3.3 AC Characteristics Table 23.12 AC Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Applicable Reference Item Symbol Pins Test Condition Min. Typ. Max. Unit Figure System clock oscillation frequency fOSC OSC1, OSC2 VCC = 4.0 to 5.5 V 2.0 20.0 MHz * 2.0 10.0 System clock (φ) cycle time tcyc 1 64 tOSC * 12.8 µs Subclock oscillation frequency fW X1, X2 32.
Section 23 Electrical Characteristics Values Applicable Item Symbol Pins Test Condition RES pin low width tREL RES At power-on and in trc modes other than those below In active mode and sleep mode operation Min. Reference Typ. Max. Unit Figure ms Figure 23.
Section 23 Electrical Characteristics Table 23.13 I2C Bus Interface Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Max. Unit Reference Figure 12tcyc + 600 ns Figure 23.
Section 23 Electrical Characteristics Table 23.14 Serial Communication Interface (SCI) Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Section 23 Electrical Characteristics 23.3.4 A/D Converter Characteristics Table 23.15 A/D Converter Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Applicable Test Symbol Pins Condition Min. Typ. Max. Unit Notes Analog power supply voltage AVCC AVCC 2.7 VCC 5.5 V * Analog input voltage AVIN AN0 to AN7 VSS – 0.3 AVCC + 0.3 V Analog power supply current AIOPE AVCC 2.0 mA Item AVCC = 5.
Section 23 Electrical Characteristics Values Applicable Test Symbol Pins Condition Item Conversion time (single mode) Min. AVCC = 4.0 to 5.5 134 V Typ. Max. Unit tcyc Nonlinearity error ±3.5 LSB Offset error ±3.5 LSB Full-scale error ±3.5 LSB Quantization error ±0.5 LSB Absolute accuracy ±4.0 LSB Notes Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
Section 23 Electrical Characteristics 23.3.6 Power-Supply-Voltage Detection Circuit Characteristics (Optional) Table 23.17 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Test Condition Power-supply falling detection voltage Vint (D) LVDSEL = 0 3.3 3.7 V Power-supply rising detection voltage Vint (U) LVDSEL = 0 4.0 4.5 V Reset detection voltage 1*1 Vreset1 LVDSEL = 0 2.3 2.
Section 23 Electrical Characteristics 23.3.7 Power-On Reset Circuit Characteristics (Optional) Table 23.18 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol Pull-up resistance of RES pin RRES Power-on reset start voltage* Vpor Note: 23.4 * Values Test Condition Min. 100 Typ. Max.
Section 23 Electrical Characteristics NMI, IRQ0 to IRQ3, WKP0 to WKP5, ADTRG, FTIOA to FTIOD, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, TMCIV, TMRIV, TRGV, FTCI, TMIB1 VIH VIL t IL t IH Figure 23.3 Input Timing VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL P* tSDAS tSCL tSDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 23.
Section 23 Electrical Characteristics t Scyc SCK3 VIH or VOH * VIL or VOL * t TXD TXD (transmit data) VOH * VOL * t RXS t RXH RXD (receive data) Note: * Output timing reference levels Output high: V OH = 2.0 V Output low: V OL = 0.8 V Load conditions are shown in figure 23.7. Figure 23.6 SCI Input/Output Timing in Clocked Synchronous Mode 23.5 Output Load Condition VCC 2.4 kΩ LSI output pin 30 pF 12 k Ω Figure 23.7 Output Load Circuit Rev. 3.00 Mar.
Section 23 Electrical Characteristics Rev. 3.00 Mar.
Appendix Appendix A. Instruction Set A.
Appendix Symbol Description ⊕ Logical exclusive OR of the operands on both sides ∼ NOT (logical complement) ( ), < > Contents of operand Symbol Description ↔ Condition Code Notation (cont) Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (
Appendix Table A.1 Instruction Set 1. Data Transfer Instructions Advanced Normal — — 0 — 2 @ERs → Rd8 — — 0 — 4 4 @(d:16, ERs) → Rd8 — — 0 — 6 8 @(d:24, ERs) → Rd8 — — 0 — 10 @ERs → Rd8 — — 0 — 6 — 4 0 — 6 0 — 8 0 — 4 0 — 6 0 — 10 0 — 6 — 4 0 — 6 0 — 8 0 — 4 0 — 2 0 — 4 0 — 6 0 — 10 0 — 6 — 6 0 — 8 0 — 4 0 — 6 0 — 10 2 2 ↔ ↔ ↔ ↔ ↔ ↔ 2 Rs8 → Rd8 ↔ ↔ ↔ ↔ ↔ ↔ B C — 0 ↔ ↔ ↔ ↔ ↔ ↔ ↔ MOV.
Appendix Condition Code Advanced 2 0 — 8 0 — 10 0 — 14 0 — 10 — 10 0 — 12 0 — 8 0 — 10 0 — 14 0 — 10 — 10 0 — 12 0 — 6 — 10 — 6 — 10 ↔ — ↔ 6 0 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ — ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ 8 0 ↔ ↔ ↔ ↔ ↔ ↔ 6 — ↔ ↔ ↔ ↔ ↔ ↔ — 0 0 0 0 — — ↔ ↔ ↔ 6 ↔ ↔ ↔ C — 0 — — ↔ V ↔ Z 0 — — ↔ N ↔ H — — 0 — — ↔ I ERd32–2 → ERd32 2 Normal — @@aa @(d, PC) Operation @aa @–ERn/@ERn+ @(d, ERn) @ERn Rn W #xx MOV.W Rs, @–ERd No.
Appendix 2. Arithmetic Instructions — (2) ↔ ↔ ↔ ↔ ↔ — (2) ↔ (3) ↔ ↔ Rd16+Rs16 → Rd16 — (1) ERd32+#xx:32 → ↔ ↔ ↔ ↔ ↔ — (1) ↔ ↔ ↔ ↔ ↔ Rd16+#xx:16 → Rd16 2 ↔ — 2 Rd8+#xx:8 +C → Rd8 — 2 B 2 Rd8+Rs8 +C → Rd8 — ↔ ↔ Rd8+Rs8 → Rd8 ↔ — Advanced C ↔ ↔ I Rd8+#xx:8 → Rd8 Normal V ↔ ↔ ↔ ↔ ↔ L Z ↔ ADD.L #xx:32, ERd N ↔ ↔ W H ↔ ↔ ADD.W Rs, Rd — W @@aa ADD.W #xx:16, Rd Condition Code @(d, PC) B No. of States*1 Operation @aa ADD.
Appendix Advanced I Normal H N Z V C DEC.L #1, ERd L 2 ERd32–1 → ERd32 — — — 2 DEC.L #2, ERd L 2 ERd32–2 → ERd32 — — ↔ ↔ — @@aa @(d, PC) @aa @–ERn/@ERn+ @(d, ERn) @ERn Rn Condition Code Operation — 2 DAS.Rd B 2 Rd8 decimal adjust — ↔ ↔ ↔ DAS No. of States*1 ↔ ↔ ↔ DEC #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) * — 2 — — — — — — 14 — — — — — — 22 * → Rd8 MULXU MULXU.
Appendix NEG.W Rd W 2 0–Rd16 → Rd16 — NEG.L ERd L 2 0–ERd32 → ERd32 — EXTU.W Rd W 2 0 → ( — — 0 — — 0 — — — — Advanced C Normal V ↔ ↔ ↔ — ↔ ↔ ↔ Z ↔ ↔ ↔ 0–Rd8 → Rd8 ↔ ↔ ↔ ↔ 2 2 0 — 2 ↔ H B 0 — 2 ↔ I NEG.B Rd 0 — 2 ↔ N ↔ ↔ ↔ — @@aa @(d, PC) @aa @–ERn/@ERn+ @(d, ERn) @ERn Rn Condition Code Operation ↔ EXTU No. of States*1 ↔ NEG #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 0 — 2 2 2 of Rd16) EXTU.
Appendix 3. Logic Instructions AND.L #xx:32, ERd L AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L NOT NOT.
Appendix 4. Shift Instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 ROTXR ROTXR.B Rd B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.
Appendix 5. Bit-Manipulation Instructions BSET BSET #xx:3, Rd B BSET #xx:3, @ERd B BSET #xx:3, @aa:8 B BSET Rn, Rd B BSET Rn, @ERd B BSET Rn, @aa:8 B BCLR BCLR #xx:3, Rd B BCLR #xx:3, @ERd B BCLR #xx:3, @aa:8 B BCLR Rn, Rd B BCLR Rn, @ERd B BCLR Rn, @aa:8 B BNOT BNOT #xx:3, Rd B No.
Appendix BST BIST B BLD #xx:3, @aa:8 B BILD #xx:3, Rd B BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BST #xx:3, @aa:8 B BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd BAND #xx:3, @ERd B BAND #xx:3, @aa:8 B BIAND BIAND #xx:3, Rd BOR BIOR B B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #xx:3
Appendix 6. Branching Instructions Bcc No.
Appendix JMP BSR JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — No.
Appendix 7. System Control Instructions Condition Code H C Advanced @@aa I Normal — @(d, PC) Operation @aa @–ERn/@ERn+ @(d, ERn) @ERn Rn No.
Appendix 8. Block Transfer Instructions EEPMOV EEPMOV. B — No. of States*1 Condition Code repeat H N Z V C — — — — — — @R5 → @R6 Advanced I 4 if R4L ≠ 0 then Normal — @@aa @(d, PC) Operation @aa @–ERn/@ERn+ @(d, ERn) @ERn Rn #xx Mnemonic Operand Size Addressing Mode and Instruction Length (bytes) 8+ 4n*2 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next EEPMOV.
REJ09B0060-0300 Rev. 3.00 Mar. 15, 2006 Page 478 of 526 MULXU 5 STC LDC 3 BVC 8 SUBX OR XOR AND MOV C D E F BILD BIST BLD BST MOV BVS 9 A B JMP BPL BMI MOV Table A.2 Table A.2 (2) (2) Table A.2 Table A.2 (2) (2) Table A.2 Table A.2 EEPMOV (2) (2) SUB ADD Table A.2 TRAPA (2) BEQ B BIAND BAND AND RTE BNE CMP BIXOR BXOR XOR BSR BCS A BIOR BOR OR RTS BCC MOV.B Table A.2 (2) LDC 7 ADDX BTST DIVXU BLS AND.B ANDC 6 9 BCLR MULXU BHI XOR.
MOV 7A BRA 58 MOV DAS 1F 79 SUBS 1B 1 ADD ADD BRN NOT 17 DEC ROTXR 13 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 CMP CMP BHI 2 SUB SUB BLS NOT ROTXR ROTXL SHLR SHLL 3 4 OR OR BCC LDC/STC 1st byte 2nd byte AH AL BH BL XOR XOR BCS DEC EXTU INC 5 AND AND BNE 6 BEQ DEC EXTU INC 7 BVC SUB NEG 9 BVS ROTR ROTL SHAR SHAL ADDS SLEEP 8 BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Table
REJ09B0060-0300 Rev. 3.00 Mar. 15, 2006 Page 480 of 526 DIVXS 3 BSET 7Faa7 * 2 BNOT BNOT BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle.
Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM — Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. See section 22.1, Register Addresses (Address Order). Rev. 3.00 Mar.
Appendix Table A.4 Number of Cycles in Each Instruction Stack Branch Addr. Read Operation K J Byte Data Access L Instruction Mnemonic Instruction Fetch I ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K BTST BTST #xx:3, Rd 1 BTST #xx:3, @ERd 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @ERd 2 1 BTST Rn, @aa:8 2 1 BXOR #xx:3, Rd 1 BXOR #xx:3, @ERd 2 1 BXOR #xx:3, @aa:8 2 1 CMP.B #xx:8, Rd 1 CMP.B Rs, Rd 1 CMP.W #xx:16, Rd 2 CMP.W Rs, Rd 1 CMP.L #xx:32, ERd 3 CMP.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K INC INC.B Rd 1 INC.W #1/2, Rd 1 INC.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K MOV MOV.B Rs, @aa:16 2 1 MOV.B Rs, @aa:24 3 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @ERs, Rd 1 1 MOV.W @(d:16,ERs), Rd 2 1 MOV.W @(d:24,ERs), Rd 4 1 MOV.W @ERs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W @aa:24, Rd 3 1 MOV.W Rs, @ERd 1 1 MOV.W Rs, @(d:16,ERd) 2 1 MOV.W Rs, @(d:24,ERd) 4 1 MOV.W Rs, @-ERd 1 1 MOV.W Rs, @aa:16 2 1 MOV.W Rs, @aa:24 3 1 MOV.L #xx:32, ERd 3 MOV.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K MULXS MULXS.B Rs, Rd 2 12 MULXS.W Rs, ERd 2 20 MULXU.B Rs, Rd 1 12 MULXU.W Rs, ERd 1 20 NEG.B Rd 1 NEG.W Rd 1 NEG.L ERd 1 NOP 1 MULXU NEG NOP NOT OR NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 OR.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K Stack ROTXR ROTXR.B Rd 1 ROTXR.W Rd 1 Byte Data Word Data Internal Access L Access M Operation N ROTXR.L ERd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAR SHLL SHLR SHAL.B Rd 1 SHAL.W Rd 1 SHAL.L ERd 1 SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 SHLR.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K SUBX SUBX #xx:8, Rd 1 SUBX. Rs, Rd 1 TRAPA TRAPA #xx:2 2 XOR XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XOR.L ERs, ERd 2 XORC #xx:8, CCR 1 XORC 1 Stack 2 Byte Data Word Data Internal Access L Access M Operation N 4 Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2.
Appendix A.4 Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes @@aa:8 — — — — — — — — — WL MOVFPE, — — — — — — — — — — — — — B BWL BWL @ERn Rn #xx — @(d:16.PC) — — @aa:24 — — BWL BWL BWL BWL BWL BWL @aa:16 — — MOV @aa:8 @(d:8.PC) @ERn+/@ERn @(d:24.ERn) — POP, PUSH Instructions Functions Data transfer instructions @(d:16.
Appendix B. I/O Ports B.1 I/O Port Block Diagrams RES goes low in a reset, and SBY goes low at reset and in standby mode. Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.1 Port 1 Block Diagram (P17) Rev. 3.00 Mar.
Appendix Internal data bus RES SBY PUCR PMR PDR PCR IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P14, P16) Rev. 3.00 Mar.
Appendix Internal data bus RES SBY Pull-up MOS PUCR PMR PDR PCR IRQ TMIB1 [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.3 Port 1 Block Diagram (P15) Internal data bus RES SBY PUCR Pull-up MOS PDR PCR [Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure B.4 Port 1 Block Diagram (P12) Rev. 3.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR 14-bit PWM PWM [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.5 Port 1 Block Diagram (P11) Rev. 3.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR RTC TMOW [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.6 Port 1 Block Diagram (P10) Internal data bus SBY PMR PDR PCR [Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure B.7 Port 2 Block Diagram (P24, P23) Rev. 3.00 Mar.
Appendix Internal data bus SBY PMR PDR PCR SCI3 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.8 Port 2 Block Diagram (P22) SBY Internal data bus PDR PCR SCI3 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.9 Port 2 Block Diagram (P21) Rev. 3.00 Mar.
Appendix SBY SCI3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.10 Port 2 Block Diagram (P20) Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.11 Port 3 Block Diagram (P37 to P30) Rev. 3.00 Mar.
Appendix Internal data bus SBY PMR PDR PCR IIC2 ICE SDAO/SCLO SDAI/SCLI [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.12 Port 5 Block Diagram (P57, P56) Rev. 3.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR ADTRG WKP5 [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.13 Port 5 Block Diagram (P55) Rev. 3.00 Mar.
Appendix Internal data bus RES SBY PUCR PMR PDR PCR WKP [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.14 Port 5 Block Diagram (P54 to P50) Rev. 3.00 Mar.
Appendix Internal data bus SBY Timer Z Output control signals A to D PDR PCR FTIOA to FTIOD [Legend] PDR: Port data register PCR: Port control register Figure B.15 Port 6 Block Diagram (P67 to P60) Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.16 Port 7 Block Diagram (P77) Rev. 3.00 Mar.
Appendix Internal data bus SBY Timer V OS3 OS2 OS1 OS0 PDR PCR TMOV [Legend] PDR: Port data register PCR: Port control register Figure B.17 Port 7 Block Diagram (P76) Internal data bus SBY PDR PCR Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register Figure B.18 Port 7 Block Diagram (P75) Rev. 3.00 Mar.
Appendix Internal data bus SBY PDR PCR Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register Figure B.19 Port 7 Block Diagram (P74) Rev. 3.00 Mar.
Appendix Internal data bus SBY PMR PDR PCR SCI3_2 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.20 Port 7 Block Diagram (P72) Internal data bus SBY PDR PCR SCI3_2 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.21 Port 7 Block Diagram (P71) Rev. 3.00 Mar.
Appendix SBY SCI3_2 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.22 Port 7 Block Diagram (P70) Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.23 Port 8 Block Diagram (P87 to P85) Rev. 3.00 Mar.
Appendix Internal data bus SBY Timer W Output control signals A to D PDR PCR FTIOA to FTIOD [Legend] PDR: Port data register PCR: Port control register Figure B.24 Port 8 Block Diagram (P84 to P81) Internal data bus SBY PDR PCR Timer W FTCI [Legend] PDR: Port data register PCR: Port control register Figure B.25 Port8 Block Diagram (P80) Rev. 3.00 Mar.
Appendix Internal data bus PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.26 Port 9 Block Diagram (P97 to P93) Internal data bus SBY SMCR PDR PCR SCI3_3 TxD [Legend] SMCR: Serial module control register PDR: Port data register PCR: Port control register Figure B.27 Port 9 Block Diagram (P92) Rev. 3.00 Mar.
Appendix SBY Internal data bus PDR PCR SCI3_3 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.28 Port 9 Block Diagram (P91) SBY SCI3_3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.29 Port 9 Block Diagram (P90) Rev. 3.00 Mar.
Appendix Internal data bus A/D converter CH3 to CH0 DEC VIN Figure B.30 Port B Block Diagram (PB7 to PB0) B.
Appendix C.
Appendix D. Package Dimensions The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority. 17.2 ± 0.3 Unit: mm 14 41 60 40 0.65 17.2 ± 0.3 61 80 21 1 0.10 *Dimension including the plating thickness Base material dimension 0.15 ± 0.04 0.83 *0.17 ± 0.05 M 2.70 0.12 3.05 Max 20 1.6 0˚ – 8˚ +0.15 0.10 –0.10 *0.32 ± 0.08 0.30 ± 0.06 0.8 ± 0.3 Package Code JEDEC JEITA Mass (reference value) FP-80A — Conforms 1.2 g Figure D.
Appendix Rev. 3.00 Mar.
Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Preface vii Added When using an on-chip emulator (E7 or E8) for H8/36049 Group program development and debugging, the following restrictions must be noted. Notes 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and P87 cannot be used. 3. Area H'FFF780 to H'FFFB7F must on no account be accessed. 4.
Item Page Revision (See Manual for Details) 6.4.1 Direct Transition from Active 86 Mode to Subactive Mode Amended Example: Direct transition time = (2 + 1) × tosc + 16 × 8 tw = 3 tosc + 128 tw (when the CPU operating clock of φosc → φw/8 is selected) 6.4.
Item Page Revision (See Manual for Details) 14.3.2 Timer Mode Register (TMDR) 221 Amended Bit Bit Name Description 0 Timer Synchronization SYNC 0: TCNT_1 and TCNT_0 operate as a different timer 1: TCNT_1 and TCNT_0 are synchronized TCNT_1 and TCNT_0 can be pre-set or cleared synchronously 14.3.7 Timer Counter (TCNT) 228 ….The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TCNT is initialized to H'0000. Figure 14.
Item Page Revision (See Manual for Details) Figure 14.44 Example of Output Disable Timing of Timer Z by Writing to TOER 276 Amended T1 T2 φ Address bus TOER address TOER Timer Z output pin Timer output I/O port Timer Z output Figure 14.45 Example of Output Disable Timing of Timer Z by External Trigger 277 I/O port Amended φ WKP4 TOER N Timer Z output pin 15.2.
Item Page Revision (See Manual for Details) 2 18.3.5 I C Bus Status Register (ICSR) 353 Amended Bit Bit Name Description 3 STOP Stop Condition Detection Flag [Setting conditions] 18.7 Usage Note 375 Added 19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) 380 Amended Figure 20.
Item Page Revision (See Manual for Details) 2 Figure 23.4 I C Bus Interface Input/Output Timing 460 Deleted VIH SDA VIL tBUF tSTAH tSCLH SCL P* S* tSf tSCLL tSr tSCL Amended Rev. 3.00 Mar. 15, 2006 Page 520 of 526 REJ09B0060-0300 H N Z V C B — * * ↔ DAA Rd Condition Code ↔ DAA No. of States*1 ↔ Mnemonic Operand Size 2. Arithmetic Instructions I Advanced 467 Normal Table A.
Index Numerics D 14-bit PWM ............................................ 295 Data reading procedure ........................... 158 Data transfer instructions .......................... 19 A A/D converter ......................................... 377 Absolute address....................................... 29 Acknowledge .......................................... 358 Address break ........................................... 63 Addressing modes.....................................
Instruction set ........................................... 18 Internal interrupts ..................................... 57 Internal power supply step-down circuit...................................................... 401 Interrupt mask bit (I)................................. 13 Interrupt response tme .............................. 59 Interval timer operation .......................... 163 IRQ3 to IRQ0 interrupts ........................... 55 L Large current ports......................................
Register indirect with displacement.......... 29 Register indirect with post-increment....... 29 Register indirect with pre-decrement........ 29 Register settings...................................... 297 Register states in each operating mode ....................................................... 417 Registers ABRKCR................ 64, 66, 409, 415, 420 ABRKSR ...................... 66, 409, 415, 420 ADCR ......................... 382, 408, 414, 420 ADCSR....................... 381, 408, 414, 420 ADDRA .
RHRDR .......................151, 405, 412, 418 RMINDR .....................150, 405, 412, 418 RSECDR......................149, 405, 412, 418 RSR .................................................... 303 RTCCR1 ......................153, 405, 412, 418 RTCCR2 ......................155, 406, 412, 418 RTCCSR......................156, 406, 412, 418 RWKDR ......................152, 405, 412, 418 SAR .............................355, 406, 413, 418 SCR3 ...........................306, 408, 414, 419 SMCR............
Trap instruction......................................... 43 V Vector address .......................................... 44 W Watchdog timer....................................... 289 Waveform output .................................... 298 Waveform output by compare match...... 241 WKP5 to WKP0 interrupts ....................... 56 Rev. 3.00 Mar.
Rev. 3.00 Mar.
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/36049 Group Publication Date: Rev.1.00, Aug. 28, 2003 Rev.3.00, Mar. 15, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8/36049 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0060-0300
