Datasheet

Section 10 Realtime Clock (RTC)
Rev. 3.00 Mar. 15, 2006 Page 156 of 526
REJ09B0060-0300
10.3.7 Clock Source Select Register (RTCCSR)
RTCCSR selects clock source. A free running counter controls start/stop of counter operation by
the RUN bit in RTCCR1. When a clock other than 32.768 kHz is selected, the RTC is disabled
and operates as an 8-bit free running counter. When the RTC operates as an 8-bit free running
counter, RSECDR enables counter values to be read. An interrupt can be generated by setting 1 to
the FOIE bit in RTCCR2 and enabling an overflow interrupt of the free running counter. A clock
in which the system clock is divided by 32, 16, 8, or 4 is output in active or sleep mode.
Bit Bit Name
Initial
Value R/W Description
7 — 0 — Reserved
This bit is always read as 0.
6
5
RCS6
RCS5
0
0
R/W
R/W
Clock Output Selection
Selects a clock output from the TMOW pin when setting
TMOW in PMR1 to 1.
00: φ/4
01: φ/8
10: φ/16
11: φ/32
4 — 0 — Reserved
This bit is always read as 0.
3
2
1
0
RCS3
RCS2
RCS1
RCS0
1
0
0
0
R/W
R/W
R/W
R/W
Clock Source Selection
0000: φ/8⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0001: φ/32⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0010: φ/128⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0011: φ/256⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0100: φ/512⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0101: φ/2048⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0110: φ/4096⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
0111: φ/8192⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅⋅ Free running counter operation
1XXX: 32.768 kHz⋅⋅⋅RTC operation
[Legend]
X: Don't care