Datasheet

Section 12 Timer V
Rev. 3.00 Mar. 15, 2006 Page 176 of 526
REJ09B0060-0300
N – 1 N H'00
φ
Compare match
A signal
Timer V output
pin
TCNTV
Figure 12.8 Clear Timing by TMRIV Input
12.5 Timer V Application Examples
12.5.1 Pulse Output with Arbitrary Duty Cycle
Figure 12.9 shows an example of output of pulses with an arbitrary duty cycle.
1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with
TCORA.
2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA
and to 0 at compare match with TCORB.
3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source.
4. With these settings, a waveform is output without further software intervention, with a period
determined by TCORA and a pulse width determined by TCORB.
Counter cleared
Time
TCNTV value
H'FF
TCORA
TCORB
H'00
TMOV
Figure 12.9 Pulse Output Example