Datasheet

Rev. 3.00 Mar. 15, 2006 Page xxi of xxxii
Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram ................................................................................................. 3
Figure 1.2 Pin Arrangements (FP-80A)..........................................................................................4
Section 2 CPU
Figure 2.1 Memory Map...............................................................................................................10
Figure 2.2 CPU Registers ............................................................................................................. 11
Figure 2.3 Usage of General Registers .........................................................................................12
Figure 2.4 Relationship between Stack Pointer and Stack Area................................................... 13
Figure 2.5 General Register Data Formats (1)..............................................................................15
Figure 2.5 General Register Data Formats (2)..............................................................................16
Figure 2.6 Memory Data Formats.................................................................................................17
Figure 2.7 Instruction Formats......................................................................................................27
Figure 2.8 Branch Address Specification in Memory Indirect Mode ........................................... 30
Figure 2.9 On-Chip Memory Access Cycle.................................................................................. 33
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)..................................... 34
Figure 2.11 CPU Operation States................................................................................................ 35
Figure 2.12 State Transitions........................................................................................................ 36
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same
Address...................................................................................................................... 37
Section 3 Exception Handling
Figure 3.1 Reset Sequence............................................................................................................ 56
Figure 3.2 Stack Status after Exception Handling ........................................................................ 58
Figure 3.3 Interrupt Sequence.......................................................................................................60
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure .............. 62
Section 4 Address Break
Figure 4.1 Block Diagram of Address Break................................................................................ 63
Figure 4.2 Address Break Interrupt Operation Example (1).........................................................67
Figure 4.2 Address Break Interrupt Operation Example (2).........................................................68
Section 5 Clock Pulse Generators
Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69
Figure 5.2 Block Diagram of System Clock Generator ................................................................70
Figure 5.3 Typical Connection to Crystal Resonator....................................................................70
Figure 5.4 Equivalent Circuit of Crystal Resonator...................................................................... 70
Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 71
Figure 5.6 Example of External Clock Input ................................................................................ 71