Datasheet

Section 13 Timer W
Rev. 3.00 Mar. 15, 2006 Page 205 of 526
REJ09B0060-0300
13.5.2 Output Compare Timing
The compare match signal is generated in the last state in which TCNT and the general register
match (when TCNT changes from the matching value to the next value). When the compare match
signal is generated, the output value selected in TIOR is output at the compare match output pin
(FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches a general register, the compare match
signal is generated only after the next counter clock pulse is input.
Figure 13.16 shows the output compare timing.
GRA to GRD
TCNT
TCNT input
clock
φ
N
N
N+1
Compare
match signal
FTIOA to FTIOD
Figure 13.16 Output Compare Output Timing