Datasheet

Rev. 3.00 Mar. 15, 2006 Page xxii of xxxii
Figure 5.7 Block Diagram of Subclock Generator ....................................................................... 72
Figure 5.8 Typical Connection to 32.768-kHz Crystal Resonator................................................ 72
Figure 5.9 Equivalent Circuit of 32.768-kHz Crystal Resonator.................................................. 72
Figure 5.10 Pin Connection when not Using Subclock ................................................................ 73
Figure 5.11 Example of Incorrect Board Design........................................................................... 74
Section 6 Power-Down Modes
Figure 6.1 Mode Transition Diagram ........................................................................................... 81
Section 7 ROM
Figure 7.1 Block Configuration of Flash Memory ....................................................................... 90
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode............................ 99
Figure 7.3 Program/Program-Verify Flowchart ......................................................................... 101
Figure 7.4 Erase/Erase-Verify Flowchart ................................................................................... 104
Section 9 I/O Ports
Figure 9.1 Port 1 Pin Configuration............................................................................................ 111
Figure 9.2 Port 2 Pin Configuration............................................................................................ 116
Figure 9.3 Port 3 Pin Configuration............................................................................................ 120
Figure 9.4 Port 5 Pin Configuration............................................................................................ 123
Figure 9.5 Port 6 Pin Configuration............................................................................................ 129
Figure 9.6 Port 7 Pin Configuration............................................................................................ 134
Figure 9.7 Port 8 Pin Configuration............................................................................................ 137
Figure 9.8 Port 9 Pin Configuration............................................................................................ 141
Figure 9.9 Port B Pin Configuration...........................................................................................145
Section 10 Realtime Clock (RTC)
Figure 10.1 Block Diagram of RTC ........................................................................................... 147
Figure 10.2 Definition of Time Expression ................................................................................ 154
Figure 10.3 Initial Setting Procedure.......................................................................................... 157
Figure 10.4 Example: Reading of Inaccurate Time Data............................................................ 158
Section 11 Timer B1
Figure 11.1 Block Diagram of Timer B1.................................................................................... 161
Section 12 Timer V
Figure 12.1 Block Diagram of Timer V ..................................................................................... 166
Figure 12.2 Increment Timing with Internal Clock.................................................................... 174
Figure 12.3 Increment Timing with External Clock................................................................... 174
Figure 12.4 OVF Set Timing...................................................................................................... 174
Figure 12.5 CMFA and CMFB Set Timing ................................................................................ 175
Figure 12.6 TMOV Output Timing ............................................................................................ 175
Figure 12.7 Clear Timing by Compare Match............................................................................ 175