Datasheet

Section 14 Timer Z
Rev. 3.00 Mar. 15, 2006 Page 246 of 526
REJ09B0060-0300
2. Input capture signal timing
Input capture on the rising edge, falling edge, or both edges can be selected through settings in
TIOR. Figure 14.18 shows the timing when the rising edge is selected. The pulse width of the
input capture signal must be at least two system clock (φ) cycles.
TCNT
Input capture signal
Input capture input
GR
N
N
φ
Figure 14.18 Input Capture Signal Timing