Datasheet

Section 14 Timer Z
Rev. 3.00 Mar. 15, 2006 Page 277 of 526
REJ09B0060-0300
2. Output Disable Timing of Timer Z by External Trigger: When P54/WKP4 is set as a WKP4
input pin, and low level is input to WKP4, the master enable bit in TOER is set to 1 and the
output of timer Z will be disabled.
WKP4
TOER
Timer Z
output pin
Timer Z output
I/O port
Timer Z output I/O port
N H'FF
φ
Figure 14.45 Example of Output Disable Timing of Timer Z by External Trigger
3. Output Inverse Timing by TFCR: The output level can be inverted by inverting the OLS1 and
OLS0 bits in TFCR in reset synchronous PWM mode or complementary PWM mode. Figure
14.46 shows the timing.
T
1
T
2
TFCR
Inverted
Timer Z
output pin
Address bus
TOER address
φ
Figure 14.46 Example of Output Inverse Timing of Timer Z by Writing to TFCR