Datasheet

Section 14 Timer Z
Rev. 3.00 Mar. 15, 2006 Page 281 of 526
REJ09B0060-0300
14.6 Usage Notes
1. Contention between TCNT Write and Clear Operations: If a counter clear signal is generated
in the T
2
state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not
performed. Figure 14.52 shows the timing in this case.
T
1
T
2
TCNT
TCNT write cycle
TCNT address
WTCNT
(internal write signal)
Clearing has priority.
Counter clear signal
N
H'0000
φ
Figure 14.52 Contention between TCNT Write and Clear Operations
2. Contention between TCNT Write and Increment Operations: If incrementation is done in T
2
state of a TCNT write cycle, TCNT writing has priority. Figure 14.53 shows the timing in this
case.
T
1
T
2
TCNT
TCNT write cycle
TCNT address
WTCNT
(internal write signal)
TCNT input clock
TCNT write data
N
M
φ
Figure 14.53 Contention between TCNT Write and Increment Operations