Datasheet

Section 14 Timer Z
Rev. 3.00 Mar. 15, 2006 Page 282 of 526
REJ09B0060-0300
3. Contention between GR Write and Compare Match: If a compare match occurs in the T
2
state
of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure
14.54 shows the timing in this case.
T
1
T
2
GR
N
M
TCNT
GR write cycle
GR address
WGR
(internal write signal)
GR write data
Compare match
signal
Disabled
N N+1
φ
Figure 14.54 Contention between GR Write and Compare Match