Datasheet

Section 14 Timer Z
Rev. 3.00 Mar. 15, 2006 Page 286 of 526
REJ09B0060-0300
7. Contention between GR Write and Input Capture: If an input capture signal is generated in the
T
2
state of a GR write cycle, the input capture operation has priority and the write to GR is not
performed. Figure 14.58 shows the timing in this case.
T
1
T
2
TCNT N
GR write cycle
GR address
Input capture
signal
WGR
(internal write signal)
Address bus
GR write data
GR M
φ
Figure 14.58 Contention between GR Write and Input Capture
8. Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode: When bits
CMD1 and CMD0 in TFCR are set, note the following:
A. Write bits CMD1 and CMD0 while TCNT_1 and TCNT_0 are halted.
B. Changing the settings of reset synchronous PWM mode to complementary PWM mode or
vice versa is disabled. Set reset synchronous PWM mode or complementary PWM mode
after the normal operation (bits CMD1 and CMD0 are cleared to 0) has been set.
9. Notes on Writing to the TOA0 to TOD0 Bits and the TOA1 to TOD1 Bits in TOCR:
The TOA0 to TOD0 bits and the TOA1 to TOD1 bits in TOCR decide the value of the FTIO
pin, which is output until the first compare match occurs. Once a compare match occurs and
this compare match changes the values of FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1
output, the values of the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pin output and the
values read from the TOA0 to TOD0 and TOA1 to TOD1 bits may differ. Moreover, when the
writing to TOCR and the generation of the compare match A0 to D0 and A1 to D1 occur at the
same timing, the writing to TOCR has the priority. Thus, output change due to the compare
match is not reflected to the FTIOA0 to FTIOD0 and FTIOA1 to FTIOD1 pins. Therefore,
when bit manipulation instruction is used to write to TOCR, the values of the FTIOA0 to
FTIOD0 and FTIOA1 to FTIOD1 pin output may result in an unexpected result. When TOCR
is to be written to while compare match is operating, stop the counter once before accessing to