Datasheet

Section 14 Timer Z
Rev. 3.00 Mar. 15, 2006 Page 287 of 526
REJ09B0060-0300
TOCR, read the port 6 state to reflect the values of FTIOA0 to FTIOD0 and FTIOA1 to
FTIOD1 output, to TOA0 to TOD0 and TOA1 to TOD1, and then restart the counter. Figure
14.59 shows an example when the compare match and the bit manipulation instruction to
TOCR occur at the same timing.
Compare match
signal B0
φ
FTIOB0 pin
TOCR
write signal
Set value
Bit
TOCR
000 00110
765 43210
TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0
Expected
output
Remains high because the 1 writing to TOB has priority
TOCR has been set to H'06. Compare match B0 and compare match C0 are used.
The FTIOB0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B0.
When BCLR#2, @TOCR is executed to clear the TOC0 bit (the FTIOC0 signal is low) and compare match B0
occurs at the same timing as shown below, the H'02 writing to TOCR has priority and compare match B0
does not drive the FTIOB0 signal low; the FTIOB0 signal remains high.
BCLR#2, @TOCR
(1) TOCR read operation: Read H'06
(2) Modify operation: Modify H'06 to H'02
(3) Write operation to TOCR: Write H'02
Figure 14.59 When Compare Match and Bit Manipulation Instruction to TOCR
Occur at the Same Timing