Datasheet

Section 15 Watchdog Timer
Rev. 3.00 Mar. 15, 2006 Page 291 of 526
REJ09B0060-0300
Bit Bit Name
Initial
Value R/W Description
2 WDON 0 R/W Watchdog Timer On
TCWD starts counting up when WDON is set to 1 and
halts when WDON is cleared to 0.
[Setting condition]
When 1 is written to the WDON bit while writing 0 to the
B2WI bit when the TCSRWE bit=1
[Clearing conditions]
• Reset by RES pin
• When 0 is written to the WDON bit while writing 0 to
the B2WI when the TCSRWE bit=1
1 B0WI 1 R/W Bit 0 Write Inhibit
This bit can be written to the WRST bit only when the
write value of the B0WI bit is 0. This bit is always read
as 1.
0 WRST 0 R/W Watchdog Timer Reset
[Setting condition]
When TCWD overflows and an internal reset signal is
generated
[Clearing conditions]
• Reset by RES pin
• When 0 is written to the WRST bit while writing 0 to
the B0WI bit when the TCSRWE bit=1