Datasheet

Section 15 Watchdog Timer
Rev. 3.00 Mar. 15, 2006 Page 292 of 526
REJ09B0060-0300
15.2.2 Timer Counter WD (TCWD)
TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the
internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to
H'00.
15.2.3 Timer Mode Register WD (TMWD)
TMWD selects the input clock.
Bit Bit Name
Initial
Value R/W Description
7 to 4  All 1  Reserved
These bits are always read as 1.
3
2
1
0
CKS3
CKS2
CKS1
CKS0
1
1
1
1
R/W
R/W
R/W
R/W
Clock Select 3 to 0
Select the clock to be input to TCWD.
1000: Internal clock: counts on φ/64
1001: Internal clock: counts on φ/128
1010: Internal clock: counts on φ/256
1011: Internal clock: counts on φ/512
1100: Internal clock: counts on φ/1024
1101: Internal clock: counts on φ/2048
1110: Internal clock: counts on φ/4096
1111: Internal clock: counts on φ/8192
0xxx: Internal oscillator
For the internal oscillator overflow periods, see section
23, Electrical Characteristics.
[Legend] x: Don't care.