Datasheet

Section 17 Serial Communication Interface 3 (SCI3)
Rev. 3.00 Mar. 15, 2006 Page 302 of 526
REJ09B0060-0300
RXD_3
input signal
Internal RXD_3 signal
in figure 17.1
Sampling clock
Sampling
clock
Internal basic clock
interval
C
Latch
Q
D
C
Latch
Q
D
C
Latch
Q
D
Match
detector
SCMR3
(NFEF_3)
Block Diagram of Noise Canceller
Clock
TXD
RXD
SCK3
TSR
RSR
TDR
SSR
SCR3
SMR
BRR
RDR
Transmit/receive
control circuit
Internal data bus
[Legend]
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter
Interrupt request
(TEI, TXI, RXI, ERI)
Internal clock (φ/64, φ/16, φ/4, φ)
External
clock
BRC
Baud rate generator
Figure 17.1 Block Diagram of SCI3