Datasheet

Section 1 Overview
Rev. 3.00 Mar. 15, 2006 Page 1 of 526
REJ09B0060-0300
Section 1 Overview
1.1 Features
• High-speed H8/300H central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 CPU on an object level
Sixteen 16-bit general registers
62 basic instructions
• Various peripheral functions
RTC (can be used as a free running counter)
Timer B1 (8-bit timer)
Timer V (8-bit timer)
Timer W (16-bit timer)
Timer Z (16-bit timer)
14-bit PWM
Watchdog timer
SCI3 (Asynchronous or clocked synchronous serial communication interface) × 3 channels
I
2
C bus interface 2 (conforms to the I
2
C bus interface format that is advocated by Philips
Electronics)
10-bit A/D converter
POR/LVD (Power-on reset and low voltage detection circuit)
• On-chip memory
Model
Product
Classification
Standard
Version
On-Chip Power-
On Reset and
Low-Voltage
Detecting Circuit
Version
ROM RAM
Flash memory version
(F-ZTAT
TM
version)
H8/36049F HD64F36049 HD64F36049G 96 kbytes 4 kbytes
Masked ROM version H8/36049 HD64336049 HD64336049G 96 kbytes 3 kbytes
H8/36048 HD64336048 HD64336048G 80 kbytes 3 kbytes
H8/36047 HD64336047 HD64336047G 64 kbytes 3 kbytes
Note: F-ZTAT
TM
is a trademark of Renesas Technology Corp.