Datasheet

Section 18 I

C Bus Interface 2 (IIC2)

Rev. 3.00 Mar. 15, 2006 Page 374 of 526

REJ09B0060-0300

18.6 Bit Synchronous Circuit

In master mode, this module has a possibility that high level period may be short in the two states

described below.

• When SCL is driven to low by the slave device

• When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pull-

up resistance)

Therefore, it monitors SCL and communicates by bit with synchronization.

Figure 18.21 shows the timing of the bit synchronous circuit and table 18.4 shows the time when

SCL output changes from low to Hi-Z then SCL is monitored.

SCL

SCL monitor

timing reference

clock

Internal SCL

Figure 18.21 Timing of Bit Synchronous Circuit

Table 18.4 Time for Monitoring SCL

CKS3 CKS2 Time for Monitoring SCL

0 7.5 tcyc 0

1 19.5 tcyc

0 17.5 tcyc 1

1 41.5 tcyc