Datasheet

Section 2 CPU
Rev. 3.00 Mar. 15, 2006 Page 31 of 526
REJ09B0060-0300
2.5.2 Effective Address Calculation
Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, a
24-bit effective address is generated.
Table 2.12 Effective Address Calculation (1)
No
1
r
o
p
31 0
23
2
3
Register indirect with dis
placement
@(d:16,ERn)
or @(d:24,ERn)
4
r
o
p
disp
r
op
rm
op
rn
3
1
0
0
r
o
p
2
3
0
31
0
dis
p
31
0
31
0
23
0
23
0
Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Register direct(Rn)
General register contents
General register contents
General register contents
General register contents
Sign extension
Register indirect(@ERn)
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
•Register indirect with pre-decrement @-ERn
1, 2, or 4
1, 2, or 4
Operand is general register contents.
The value to be added or subtracted is 1 when the
operand is byte size, 2 for word size, and 4 for
longword size.