Datasheet
Section 3 Exception Handling
Rev. 3.00 Mar. 15, 2006 Page 52 of 526
REJ09B0060-0300
3.2.6 Interrupt Flag Register 2 (IRR2)
IRR2 is a status flag register for timer B1 overflow interrupts.
Bit Bit Name
Initial
Value R/W Description
7
6
0
0
Reserved
These bits are always read as 0.
5 IRRTB1 0 R/W Timer B1 Interrupt Request flag
[Setting condition]
When the timer B1 counter value overflows
[Clearing condition]
When IRRTB1 is cleared by writing 0
4
3
2
1
0
1
1
1
1
1
Reserved
These bits are always read as 1.