Datasheet

Section 3 Exception Handling
Rev. 3.00 Mar. 15, 2006 Page 60 of 526
REJ09B0060-0300
φ Internal address bus Internal read signal Internal write signal Internal data bus Interrupt request signal
(14)
(12)(10)(6)
(4)
High
(2)
(1) (5) (7) (9) (11)
(13)
Instruction prefetch of interrupt handling routine
Internal
processing
Vector fetchStack
Instruction
prefetch
Internal
processing
Interrupt level decision and wait for end of instruction
Interrupt
accepted
(3)
(1) (2), (4) (3) (5) (7)
Instruction prefetch address (not executed; return address, same as PC contents) Instruction code (not executed) Instruction prefetch address (not executed) SP – 2 SP – 4
PC and CCR saved to stack Vector address Starting address of interrupt handling routine (contents of vector address) Starting address of interrupt handling routine; (13) = (10), (12) First instruction of interrupt handling routine
(6), (8) (9), (11) (10), (12) (13) (14)
(8)
Figure 3.3 Interrupt Sequence