To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual 16 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
Rev. 4.00 Mar.
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface The H8/36057 Group and H8/36037 Group are single-chip microcomputers made up of the highspeed H8/300H CPU employing Renesas Technology-original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/36057 Group and H8/36037 Group in the design of application systems.
Notes: When using an on-chip emulator (E7, E8) for H8/36057 and H8/36037 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be provided on the user board. 3. Area H'D000 to H'DFFF is used by the E7 or E8, and is not available to the user. 4. Area H'F780 to H'FB7F must on no account be accessed. 5.
Application notes: Document Title Document No. H8S, H8/300 Series C/C++ Compiler Package Application Note TM Single Power Supply F-ZTAT On-Board Programming Rev. 4.00 Mar.
Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features................................................................................................................................. 1 Internal Block Diagram......................................................................................................... 3 Pin Arrangement ....................................................................................
3.3 3.4 3.5 3.2.4 Interrupt Enable Register 2 (IENR2) .................................................................. 55 3.2.5 Interrupt Flag Register 1 (IRR1)......................................................................... 55 3.2.6 Interrupt Flag Register 2 (IRR2)......................................................................... 57 3.2.7 Wakeup Interrupt Flag Register (IWPR) ............................................................ 57 Reset Exception Handling .......................
6.2 6.3 6.4 6.5 Mode Transitions and States of LSI.................................................................................... 82 6.2.1 Sleep Mode ......................................................................................................... 84 6.2.2 Standby Mode ..................................................................................................... 84 6.2.3 Subsleep Mode....................................................................................................
9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.1.4 Port Pull-Up Control Register 1 (PUCR1)........................................................ 114 9.1.5 Pin Functions .................................................................................................... 114 Port 2................................................................................................................................. 116 9.2.1 Port Control Register 2 (PCR2) .....................................................................
10.5 10.4.1 Interval Timer Operation .................................................................................. 147 10.4.2 Auto-Reload Timer Operation .......................................................................... 147 10.4.3 Event Counter Operation .................................................................................. 147 Timer B1 Operating Modes .............................................................................................. 148 Section 11 Timer V............
12.5 12.6 12.4.1 Counter Operation ............................................................................................ 187 12.4.2 Waveform Output by Compare Match.............................................................. 191 12.4.3 Input Capture Function ..................................................................................... 195 12.4.4 Synchronous Operation..................................................................................... 198 12.4.5 PWM Mode ..................
14.6 14.7 14.8 14.5.1 Clock................................................................................................................. 278 14.5.2 SCI3 Initialization............................................................................................. 278 14.5.3 Serial Data Transmission .................................................................................. 279 14.5.4 Serial Data Reception (Clocked Synchronous Mode)....................................... 281 14.5.
15.4.1 15.4.2 15.5 15.6 15.7 15.8 15.9 Message Control (MCn0, MCn4 to MCn7 [n = 0 to 3]) ................................... 319 Local Acceptance Filter Mask (LAFMHn1, LAFMHn0, LAFMLn1, LAFMLn0 [n = 0 to 3]) ........................ 322 15.4.3 Message Data (MDn0 to MDn7 [n = 0 to 3]) ................................................... 323 Operation .......................................................................................................................... 324 15.5.
16.5 16.4.11 Interrupt Requests ............................................................................................. 377 Usage Note........................................................................................................................ 378 Section 17 Subsystem Timer (Subtimer) ...........................................................379 17.1 17.2 17.3 17.4 17.5 Features.............................................................................................................
19.3.1 19.3.2 Power-On Reset Circuit .................................................................................... 408 Low-Voltage Detection Circuit......................................................................... 409 Section 20 Power Supply Circuit ...................................................................... 413 20.1 20.2 When Using Internal Power Supply Step-Down Circuit ..................................................
Appendix B I/O Port Block Diagrams ...............................................................517 B.1 B.2 I/O Port Block Diagrams .................................................................................................. 517 Port States in Each Operating State .................................................................................. 544 Appendix C Product Code Lineup.....................................................................545 Appendix D Package Dimensions .................
Rev. 4.00 Mar.
Figures Section 1 Overview Figure 1.1 Internal Block Diagram of F-ZTAT TM and Masked ROM Versions ............................ 3 Figure 1.2 Pin Arrangement of F-ZTATTM and Masked ROM Versions (FP-64K, FP-64A)......... 4 Section 2 CPU Figure 2.1 Memory Map (1) ......................................................................................................... 11 Figure 2.1 Memory Map (2) .........................................................................................................
Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 75 Figure 5.6 Example of External Clock Input ................................................................................ 75 Figure 5.7 Example of Incorrect Board Design ............................................................................ 76 Section 6 Power-Down Modes Figure 6.1 Mode Transition Diagram ..............................................................................
Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Timer Z Timer Z Block Diagram .......................................................................................... 165 Timer Z (Channel 0) Block Diagram ...................................................................... 166 Timer Z (Channel 1) Block Diagram ...................................................................... 167 Example of Outputs in Reset Synchronous PWM Mode and Complementary PWM Mode .................................
Figure 12.36 Input Capture Buffer Operation............................................................................. 221 Figure 12.37 Example of Buffer Operation Setting Procedure................................................... 222 Figure 12.38 Example of Buffer Operation (1) (Buffer Operation for Output Compare Register) ................................................. 223 Figure 12.39 Example of Compare Match Timing for Buffer Operation ................................... 224 Figure 12.
Figure 14.5 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 272 Figure 14.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 273 Figure 14.7 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 274 Figure 14.
Figure 15.15 Figure 15.16 Figure 15.17 Figure 15.18 Set Timing for Message Reception ....................................................................... 338 RXPR/RFPR Set/Clear Timing when Overrun/Overwrite Occurs........................ 339 Flowchart for Changing ID, MBCR, and LAFM of Receive Mailbox.................. 341 Flowchart for Transition between Active Mode and Standby Mode or Module Standby Mode .................................................................................................
Figure 19.4 Operational Timing of LVDI Circuit....................................................................... 411 Figure 19.5 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 412 Section 20 Power Supply Circuit Figure 20.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 413 Figure 20.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 414 Section 22 Figure 22.1 Figure 22.2 Figure 22.
Figure B.17 Figure B.18 Figure B.19 Figure B.20 Figure B.21 Figure B.22 Figure B.23 Figure B.24 Figure B.25 Figure B.26 Figure B.27 Port 7 Block Diagram (P71) ................................................................................... 533 Port 7 Block Diagram (P70) ................................................................................... 534 Port 8 Block Diagram (P87 to P85) ........................................................................ 535 Port 9 Block Diagram (P97) ...........
Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 5 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 21 Table 2.2 Data Transfer Instructions....................................................................................... 22 Table 2.3 Arithmetic Operations Instructions (1) ...............................
Table 7.3 Table 7.4 Table 7.5 Table 7.6 Table 7.7 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible................................................................................................................... 98 Reprogram Data Computation Table .................................................................... 102 Additional-Program Data Computation Table ...................................................... 102 Programming Time ...................................
Table 15.4 Table 15.5 Interrupt Requests ................................................................................................. 344 Test Mode Settings ............................................................................................... 345 Section 16 Synchronous Serial Communication Unit (SSU) Table 16.1 Pin Configuration.................................................................................................. 349 Table 16.
Appendix A Table A.1 Table A.2 Table A.2 Table A.2 Table A.3 Table A.4 Table A.5 Instruction Set Instruction Set....................................................................................................... 489 Operation Code Map (1) ....................................................................................... 502 Operation Code Map (2) ....................................................................................... 503 Operation Code Map (3) ......................................
Section 1 Overview Section 1 Overview 1.
Section 1 Overview • On-chip memory Model Standard Version On-Chip PowerOn Reset and Low-Voltage Detecting Circuit Version ROM RAM H8/36057F HD64F36057 HD64F36057G 56 kbytes 3 kbytes H8/36054F HD64F36054 HD64F36054G 32 kbytes 2 kbytes H8/36037F HD64F36037 HD64F36037G 56 kbytes 3 kbytes H8/36034F HD64F36034 HD64F36034G 32 kbytes 2 kbytes H8/36057 HD64336057 HD64336057G 56 kbytes 2 kbytes H8/36054 HD64336054 HD64336054G 32 kbytes 2 kbytes H8/36037 HD64336037 HD64336037G 5
Section 1 Overview Internal oscillator P57 P56 P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 NMI TEST RES VSS VCC Port 6 P76/TMOV P75/TMCIV P74/TMRIV P72/TXD_2*2 P71/RXD_2*2 P70/SCK3_2*2 Port 1 P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 Port 7 Data bus (lower) RAM ROM SSU TinyCAN SCI3 Subtimer SCI3_2*1 Timer Z Watchdog timer Timer V Timer B1 A/D converter POR and LVD*3 Port 8 P90/SCS P91/SSCK P92/SSO P93/SSI P94 P95 P96/HRx
Section 1 Overview P62/FTIOC0 P61/FTIOB0 NMI P60/FTIOA0 P64/FTIOA1 P65/FTIOB1 P66/FTIOC1 P67/FTIOD1 P85 P86 P87 P20/SCK3 P21/RXD P22/TXD P23 Pin Arrangement P70/SCK3_2*2 1.
Section 1 Overview 1.4 Pin Functions Table 1.1 Pin Functions Pin No. Type Symbol FP-64K FP-64A I/O Functions Power source pins VCC 12 Input Power supply pin. Connect this pin to the system power supply. VSS 9 Input Ground pin. Connect this pin to the system power supply (0 V). AVCC 3 Input Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply. VCL 6 Input Internal step-down power supply pin.
Section 1 Overview Pin No. Type Symbol FP-64K FP-64A I/O Functions Timer Z FTIOA0 36 I/O Output compare output/input capture input/external clock input pin. FTIOB0 34 I/O Output compare output/input capture input/PWM output pin. FTIOC0 33 I/O Output compare output/input capture input/PWM sync output pin (at a reset, complementary PWM mode). FTIOD0 32 I/O Output compare output/input capture input/PWM output pin.
Section 1 Overview Pin No. Type Symbol I/O ports Note: * FP-64K FP-64A I/O Functions PB7 to PB0 1, 2, 59 to 64 Input 8-bit input ports. P17 to P14, 51 to 54, P12 to P10 23 to 25 I/O 7-bit I/O ports. P24 to P20 31, 44 to 47 I/O 5-bit I/O ports. P57 to P50 13, 14, 19 to 22, 26, 27 I/O 8-bit I/O ports. P67 to P60 32 to 34, I/O 36, 37 to 40 8-bit I/O ports. P76 to P74, 28 to 30, P72 to P70 48 to 50 I/O 6-bit I/O ports. P87 to P85 41 to 43 I/O 3-bit I/O ports.
Section 1 Overview Rev. 4.00 Mar.
Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added.
Section 2 CPU • Power-down state Transition to power-down state by SLEEP instruction 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map. Rev. 4.00 Mar.
Section 2 CPU HD64F36054 HD64F36054G HD64F36034 HD64F36034G (Flash memory version) HD64F36057 HD64F36057G HD64F36037 HD64F36037G (Flash memory version) H'0000 H'0049 H'004A Interrupt vector H'0000 H'0049 H'004A Interrupt vector On-chip ROM (32 kbytes) H'7FFF On-chip ROM (56 kbytes) Not used H'DFFF Not used H'EC00 H'EFFF On-chip RAM (1 kbyte) Not used H'F600 H'F77F H'F780 H'FB7F H'FB80 H'FF7F H'FF80 Internal I/O register (1-kbyte work area for flash memory programming) On-chip RAM (2 kbytes) (1
Section 2 CPU HD64336054G HD64336054 (Masked ROM version) HD64336057G HD64336057 (Masked ROM version) H'0000 H'0049 H'004A Interrupt vector H'0000 H'0049 H'004A Interrupt vector HD64336037G HD64336037 (Masked ROM version) H'0000 H'0049 H'004A Interrupt vector HD64336036G HD64336036 (Masked ROM version) H'0000 H'0049 H'004A On-chip ROM (32 kbytes) Interrupt vector On-chip ROM (48 kbytes) H'7FFF On-chip ROM (56 kbytes) On-chip ROM (56 kbytes) H'BFFF Not used H'DFFF Not used H'EC00 H'EFFF No
Section 2 CPU HD64336035G HD64336035 (Masked ROM version) H'0000 H'0049 H'004A Interrupt vector HD64336033G HD64336033 (Masked ROM version) HD64336034G HD64336034 (Masked ROM version) H'0000 H'0049 H'004A Interrupt vector H'0000 H'0049 H'004A On-chip ROM (24 kbytes) On-chip ROM (32 kbytes) On-chip ROM (40 kbytes) Interrupt vector HD64336032G HD64336032 (Masked ROM version) H'0000 H'0049 H'004A Interrupt vector On-chip ROM (16 kbytes) H'3FFF H'5FFF H'7FFF H'9FFF Not used Not used Not used
Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition-code register (CCR).
Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Empty area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0).
Section 2 CPU Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.
Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers.
Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data 0 LSB 0 LSB ERn 31 16 15 MSB 0 LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev. 4.00 Mar.
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.
Section 2 CPU Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers/address register (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) → Rd Cannot be used in this LSI.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd) Transfers the CCR contents to a destination location.
Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. Rev. 4.00 Mar.
Section 2 CPU 2.4.2 Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction formats. • Operation Field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction.
Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.10. Each instruction uses a subset of these addressing modes. Addressing modes that can be used differ depending on the instruction. For details, refer to appendix A.
Section 2 CPU (2) Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum the address of a memory operand.
Section 2 CPU Table 2.11 Absolute Address Access Ranges Absolute Address Access Range 8 bits (@aa:8) H'FF00 to H'FFFF 16 bits (@aa:16) H'0000 to H'FFFF 24 bits (@aa:24) H'0000 to H'FFFF (6) Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly.
Section 2 CPU Specified by @aa:8 Dummy Branch address Figure 2.8 Branch Address Specification in Memory Indirect Mode Rev. 4.00 Mar.
Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents.
Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op abs 0 H'FFFF @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 0 23 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states.
Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states, three states, or four states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 21.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8bit data bus width can be accessed by byte or word size.
Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state, there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes.
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Interrupt source Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.12 State Transitions Rev. 4.00 Mar.
Section 2 CPU 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data is transferred from CPU to empty areas, the transferred data will be lost. This action may also cause the CPU to malfunction. When data is transferred from an empty area to CPU, the contents of the data cannot be guaranteed. 2.8.
Section 2 CPU The timer is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer counter may be modified and the modified value may be written to the timer load register. Read Count clock Timer counter Reload Write Timer load register Internal data bus Figure 2.13 Example of Timer Configuration with Two Registers Allocated to Same Address Example 2: The BSET instruction is executed for port 5.
Section 2 CPU • After executing BSET instruction P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 0 0 1 1 1 1 1 1 PDR5 0 1 0 0 0 0 0 1 • Description on operation 1. When the BSET instruction is executed, first the CPU reads port 5.
Section 2 CPU • BSET instruction executed BSET #0, @RAM0 The BSET instruction is executed designating the PDR5 work area (RAM0). • After executing BSET instruction MOV.B MOV.B @RAM0, R0L R0L, @PDR5 P57 The work area (RAM0) value is written to PDR5.
Section 2 CPU • BCLR instruction executed BCLR #0, @PCR5 The BCLR instruction is executed for PCR5. • After executing BCLR instruction P57 P56 P55 P54 P53 P52 P51 P50 Input/output Output Output Output Output Output Output Output Input Pin state Low level High level Low level Low level Low level Low level Low level High level PCR5 1 1 1 1 1 1 1 0 PDR5 1 0 0 0 0 0 0 0 • Description on operation 1. When the BCLR instruction is executed, first the CPU reads PCR5.
Section 2 CPU • BCLR instruction executed BCLR #0, @RAM0 The BCLR instructions executed for the PCR5 work area (RAM0). • After executing BCLR instruction MOV.B MOV.B @RAM0, R0L R0L, @PCR5 The work area (RAM0) value is written to PCR5.
Section 2 CPU Rev. 4.00 Mar.
Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin.
Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table 3.
Section 3 Exception Handling Vector Number Vector Address Priority Compare match/input capture A0 to D0 Timer Z overflow 26 H'0034 to H'0035 High Compare match/input capture A1 to D1 Timer Z overflow Timer Z underflow 27 H'0036 to H'0037 Relative Module Exception Sources Timer Z Timer B1 Timer B1 overflow 29 H'003A to H'003B SCI3_2*2 Receive data full Transmit data empty Transmit end Receive error 32 H'0040 to H'0041 TinyCAN Error 34 Reset/HALT mode processing Message reception Messag
Section 3 Exception Handling 3.2 Register Descriptions Interrupts are controlled by the following registers. • • • • • • • Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt enable register 2 (IENR2) Interrupt flag register 1 (IRR1) Interrupt flag register 2 (IRR2) Wakeup interrupt flag register (IWPR) 3.2.
Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Bit Bit Name Initial Value R/W Description 7, 6 All 1 Reserved These bits are always read as 1.
Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts and external pin interrupts. Bit Bit Name Initial Value R/W Description 7 IENDT 0 R/W Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6 0 Reserved This bit is always read as 1. 5 IENWP 0 R/W Wakeup Interrupt Enable This bit is an enable bit, which is common to the pins WKP5 to WKP0.
Section 3 Exception Handling 3.2.4 Interrupt Enable Register 2 (IENR2) IENR2 enables, timer B1 overflow interrupts. Bit Bit Name Initial Value R/W 7, 6 All 0 Description Reserved These bits are always read as 0. 5 IENTB1 0 R/W 4 to 0 All 1 Timer B1 Interrupt Enable When this bit is set to 1, timer B1 overflow interrupt requests are enabled. Reserved These bits are always read as 1.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 3 IRRI3 0 R/W IRQ3 Interrupt Request Flag [Setting condition] When IRQ3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI3 is cleared by writing 0 2 IRRI2 0 R/W IRQ2 Interrupt Request Flag [Setting condition] When IRQ2 pin is designated for interrupt input and the designated signal edge is detected.
Section 3 Exception Handling 3.2.6 Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 overflow interrupts. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. 5 IRRTB1 0 R/W Timer B1 Interrupt Request flag [Setting condition] When the timer B1 counter value overflows [Clearing condition] When IRRTB1 is cleared by writing 0 4 to 0 All 1 Reserved These bits are always read as 1. 3.2.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 3 IWPF3 0 R/W WKP3 Interrupt Request Flag [Setting condition] When WKP3 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF3 is cleared by writing 0. 2 IWPF2 0 R/W WKP2 Interrupt Request Flag [Setting condition] When WKP2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF2 is cleared by writing 0.
Section 3 Exception Handling 3.3 Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure that this LSI is reset at power-up, hold the RES pin low until the clock pulse generator output stabilizes. To reset the chip during operation, hold the RES pin low for at least 10 system clock cycles.
Section 3 Exception Handling 3.4 Interrupt Exception Handling 3.4.1 External Interrupts As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts. NMI Interrupt: NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1. NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit value in CCR.
Section 3 Exception Handling Reset cleared Initial program instruction prefetch Vector fetch Internal processing RES φ Internal address bus (1) (2) Internal read signal Internal write signal Internal data bus (16 bits) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.1 Reset Sequence 3.4.
Section 3 Exception Handling 3.4.3 Interrupt Handling Sequence Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows. 1. If an interrupt occurs while the NMI or interrupt enable bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1.
Section 3 Exception Handling SP – 4 SP (R7) CCR SP – 3 SP + 1 CCR*3 SP – 2 SP + 2 PCH SP – 1 SP + 3 PCL SP (R7) SP + 4 Even address Stack area Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling [Legend] PCH : Upper 8 bits of program counter (PC) PCL : Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1.
REJ09B0026-0400 Rev. 4.00 Mar. 15, 2006 Page 64 of 556 Figure 3.3 Interrupt Sequence (2) (1) (4) Instruction prefetch (3) Internal processing (5) (1) Stack access (6) (7) (9) Vector fetch (8) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.
Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Section 3 Exception Handling Rev. 4.00 Mar.
Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit in CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Section 4 Address Break 4.1 Register Descriptions The address break has the following registers. • • • • Address break control register (ABRKCR) Address break status register (ABRKSR) Break address register (BARH, BARL) Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions.
Section 4 Address Break Bit Bit Name Initial Value R/W Description 1 DCMP1 0 R/W Data Compare Condition Select 1 and 0 0 DCMP0 0 R/W These bits set the comparison condition between the data set in BDR and the internal data bus. 00: No data comparison 01: Compares lower 8-bit data between BDRL and data bus 10: Compares upper 8-bit data between BDRH and data bus 11: Compares 16-bit data between BDR and data bus [Legend] X: Don't care.
Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Bit Bit Name Initial Value R/W Description 7 ABIF 0 R/W Address Break Interrupt Flag [Setting condition] When the condition set in ABRKCR is satisfied [Clearing condition] When 0 is written after ABIF=1 is read 6 ABIE 0 R/W Address Break Interrupt Enable When this bit is 1, an address break interrupt request is enabled.
Section 4 Address Break 4.2 Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set to 1 by the combination of the address set in BAR, the data set in BDR, and the conditions set in ABRKCR. When the interrupt request is accepted, interrupt exception handling starts after the instruction being executed ends. The address break interrupt is not masked by the I bit in CCR of the CPU. Figures 4.
Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A Program 0258 025A * 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP Underline indicates the address NOP to be stacked.
Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators The clock pulse generator is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and a system clock divider. The subclock pulse generator consists of an on-chip oscillator, division ratio setting register, and a sub-clock divider. Figure 5.1 shows a block diagram of the clock pulse generators.
Section 5 Clock Pulse Generators 5.1 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system clock generator. OSC 2 LPM OSC 1 LPM: Low-power mode (standby mode, subactive mode, subsleep mode) Figure 5.2 Block Diagram of System Clock Generator 5.1.1 Connecting Crystal Resonator Figure 5.
Section 5 Clock Pulse Generators Table 5.1 Crystal Resonator Parameters Frequency (MHz) 2 4 8 10 16 20 RS (max) 500 Ω 120 Ω 80 Ω 60 Ω 50 Ω 40 Ω C0 (max) 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator. C1 OSC1 C2 OSC2 C1 = C2 = 5 to 30 pF Figure 5.5 Typical Connection to Ceramic Resonator 5.1.3 External Clock Input Method Connect an external clock signal to pin OSC1, and leave pin OSC2 open.
Section 5 Clock Pulse Generators 5.2 Prescaler 5.2.1 Prescaler S Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S.
Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting on-chip module functions. • Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are listed below. • • • • System control register 1 (SYSCR1) System control register 2 (SYSCR2) Module standby control register 1 (MSTCR1) Module standby control register 2 (MSTCR2) 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2.
Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time Bit Name Operating Frequency STS2 STS1 STS0 Waiting Time 0 0 1 1 0 1 20 MHz 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 0 8,192 states 0.4 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 states 0.8 1.0 1.6 2.0 4.1 8.2 16.4 32.8 0 32,768 states 1.6 2.0 3.3 4.1 8.2 16.4 32.8 65.5 1 65,536 states 3.3 4.1 6.6 8.2 16.4 32.8 65.5 131.1 0 131,072 states 6.6 8.2 13.1 16.4 32.8 65.5 131.
Section 6 Power-Down Modes Bit Bit Name Initial Value R/W Description 1 SA1 0 R/W Subactive Mode Clock Select 1 and 0 0 SA0 0 R/W These bits select the operating clock frequency in subactive and subsleep modes. The operating clock frequency changes to the set frequency after the SLEEP instruction is executed. 00: φW/8 01: φW/4 1X: φW/2 [Legend] X: Don't care. 6.1.
Section 6 Power-Down Modes 6.1.4 Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W Description 7 MSTS3_2 0 R/W SCI3_2 Module Standby The SCI3_2 enters standby mode when this bit is set to 1. Note: This bit is reserved in the H8/36037 Group. This bit is always read as 0. 6, 5 All 0 Reserved These bits are always read as 0.
Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state. A direct transition between active mode and subactive mode, which are both program execution states, can be made without halting the program.
Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode due to Interrupt DTON SSBY SMSEL LSON Transition Mode after SLEEP Instruction Execution 0 0 0 0 Sleep mode 1 1 Active mode Subactive mode 0 Subsleep mode Active mode 1 1 Transition Mode due to Interrupt Subactive mode 1 X X Standby mode Active mode X 0* 0 Active mode (direct transition) — X X 1 Subactive mode (direct transition) — [Legend] X: Don’t care.
Section 6 Power-Down Modes Active Mode Sleep Mode Subactive Mode Subsleep Mode Standby Mode Timer V Functioning Functioning Reset Reset Reset Watchdog timer Functioning Functioning Retained (functioning if the internal oscillator are selected as a count clock*) SCI3, SCI3_2* Functioning Functioning Reset Reset Reset TinyCAN Functioning Functioning Retained Retained Retained SSU Functioning Functioning Retained Retained Retained Subtimer Functioning Functioning Functioning
Section 6 Power-Down Modes Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, and interrupt exception handling starts. Standby mode is not cleared if the I bit of CCR is set to 1 or the requested interrupt is disabled in the interrupt enable register. When the RES pin goes low, the system clock pulse generator starts.
Section 6 Power-Down Modes 6.3 Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction execution. 6.4 Direct Transition The CPU can execute programs in two modes: active and subactive modes. A direct transition is a transition between these two modes without stopping program execution.
Section 6 Power-Down Modes 6.4.2 Direct Transition from Subactive Mode to Active Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2).
Section 6 Power-Down Modes Rev. 4.00 Mar.
Section 7 ROM Section 7 ROM The features of the 56-kbyte or 32-kbyte flash memories built into the flash memory (F-ZTAT) version are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
Section 7 ROM Erase unit H'0000 H'0001 H'0002 H'0080 H'0081 H'0082 H'0380 H'0381 H'0382 H'0400 H'0401 H'0402 H'0480 H'0481 H'0481 H'0780 H'0781 H'0782 H'0800 H'0801 H'0802 H'0880 H'0881 H'0882 H'0B80 H'0B81 H'0B82 H'0C00 H'0C01 H'0C02 H'0C80 H'0C81 H'0C82 H'0F80 H'0F81 H'0F82 H'1000 H'1001 H'1002 H'1080 H'1081 H'1082 Programming unit: 128 bytes H'007F H'00FF 1 kbyte Erase unit H'03FF Programming unit: 128 bytes H'047F H'04FF 1 kbyte Erase unit H'07FF Progr
Section 7 ROM 7.2 Register Descriptions The flash memory has the following registers. • • • • • Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory power control register (FLPWCR) Flash memory enable register (FENR) 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode.
Section 7 ROM Bit Bit Name Initial Value R/W Description 2 PV 0 R/W Program-Verify When this bit is set to 1, the flash memory changes to program-verify mode. When it is cleared to 0, programverify mode is cancelled. 1 E 0 R/W Erase When this bit is set to 1 while SWE = 1 and ESU = 1, the flash memory changes to erase mode. When it is cleared to 0, erase mode is cancelled. 0 P 0 R/W Program When this bit is set to 1 while SWE = 1 and PSU = 1, the flash memory changes to program mode.
Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7 — 0 — Reserved This bit is always read as 0. 6 EB6 0 R/W When this bit is set to 1, 8 bytes of H'C000 to H'DFFF will be erased.
Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Section 7 ROM 7.3 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1.
Section 7 ROM 7.3.1 Boot Mode Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 7.4, Flash Memory Programming/Erasing. 2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop bit, and no parity. 3.
Section 7 ROM Boot Mode Operation Host Operation Communication Contents Processing Contents Transfer of number of bytes of programming control program Flash memory erase Bit rate adjustment Boot mode initiation Item Table 7.2 LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 . . .
Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 16 to 20 MHz 9,600 bps 8 to 16 MHz 4,800 bps 4 to 16 MHz 2,400 bps 2 to 16 MHz 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program.
Section 7 ROM Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode Rev. 4.00 Mar.
Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing.
Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 — 1 1 1 Remains in erased state Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Additional-Program Data Comments 0 0 0 Additional-program bit 0 1 1 No additional programming 1 0 1 No additional programming 1 1 1 No additional programming Comments Table 7.
Section 7 ROM 7.4.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR1). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n←1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 0 Wait 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs * n←n+1 Read verify data No Verify data + all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4 µs All erase block erased ? n ≤ 100 ? Yes Yes No Yes SWE bit ← 0
Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode.
Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be reentered by re-setting the P or E bit. However, PV and EV bit settings are retained, and a transition can be made to verify mode. Error protection can be cleared only by a power-on reset. 7.
Section 7 ROM Table 7.7 Flash Memory Operating States Flash Memory Operating State LSI Operating State PDWND = 0 (Initial Value) PDWND = 1 Active mode Normal operating mode Normal operating mode Subactive mode Power-down mode Normal operating mode Sleep mode Normal operating mode Normal operating mode Subsleep mode Standby mode Standby mode Standby mode Standby mode Standby mode Rev. 4.00 Mar.
Section 7 ROM Rev. 4.00 Mar.
Section 8 RAM Section 8 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
Section 8 RAM Rev. 4.00 Mar.
Section 9 I/O Ports Section 9 I/O Ports This LSI has forty-five general I/O ports and eight general input-only ports. Port 6 is a large current port, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset. They can also be used as I/O pins of the on-chip peripheral modules or external interrupt input pins, and these functions can be switched depending on the register settings.
Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W Description 7 IRQ3 0 R/W This bit selects the function of pin P17/IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6 IRQ2 0 R/W This bit selects the function of pin P16/IRQ2. 0: General I/O port 1: IRQ2 input pin 5 IRQ1 0 R/W This bit selects the function of pin P15/IRQ1/TMIB1.
Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W Description 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR14 0 W Bit 3 is a reserved bit.
Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7 PUCR17 0 R/W Only bits for which PCR1 is cleared are valid. 6 PUCR16 0 R/W 5 PUCR15 0 R/W 4 PUCR14 0 R/W The pull-up MOS of the corresponding pins enters the onstate when these bits are set to 1, while they enter the off-state when these bits are cleared to 0.
Section 9 I/O Ports • P16/IRQ2 pin Register PMR1 PCR1 Bit Name IRQ2 PCR16 Pin Function Setting value 0 0 P16 input pin 1 P16 output pin X IRQ2 input pin 1 [Legend] X: Don't care. • P15/IRQ1/TMIB1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Pin Function Setting value 0 0 P15 input pin 1 P15 output pin X IRQ1 input/TMIB1 input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports • P11 pin Register PCR1 Bit Name PCR11 Pin Function Setting value 0 P11 input pin 1 P11 output pin • P10 pin Register PCR1 Bit Name PCR10 Pin Function Setting value 0 P10 input pin 1 P10 output pin 9.2 Port 2 Port 2 is a general I/O port also functioning as SCI3 I/O pins. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1and SCI3 have priority for functions of the pins for both uses. P24 P23 Port 2 P22/TXD P21/RXD P20/SCK3 Figure 9.
Section 9 I/O Ports 9.2.1 Port Control Register 2 (PCR2) PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2. Bit Bit Name Initial Value R/W 7 to 5 Reserved 4 PCR24 0 W 3 PCR23 0 W 2 PCR22 0 W When each of the port 2 pins P24 to P20 functions as a general I/O port, setting a PCR2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 1 PCR21 0 W 0 PCR20 0 W 9.2.
Section 9 I/O Ports 9.2.3 Port Mode Register 3 (PMR3) PMR3 selects the CMOS output or NMOS open-drain output for port 2. Bit Bit Name Initial Value R/W Description 7 to 5 All 0 Reserved These bits are always read as 0. 4 POF24 0 R/W 3 POF23 0 R/W When the bit is set to 1, the corresponding pin is cut off by PMOS and it functions as the NMOS open-drain output. When cleared to 0, the pin functions as the CMOS output. 2 to 0 All 1 Reserved These bits are always read as 1. 9.
Section 9 I/O Ports • P22/TXD pin Register PMR1 PCR2 Bit Name TXD PCR22 Pin Function Setting Value 0 0 P22 input pin 1 P22 output pin X TXD output pin 1 [Legend] X: Don't care. • P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Pin Function Setting Value 0 0 P21 input pin 1 P21 output pin X RXD input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports 9.3 Port 5 Port 5 is a general I/O port also functioning as an A/D trigger input pin and a wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting of the I2C bus interface register has priority for functions of the pins P57/SCL and P56/SDA.
Section 9 I/O Ports 9.3.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W Description 7 POF57 0 R/W 6 POF56 0 R/W When the bit is set to 1, the corresponding pin is cut off by PMOS and it functions as the NMOS open-drain output. When cleared to 0, the pin functions as the CMOS output. 5 WKP5 0 R/W This bit selects the function of pin P55/WKP5/ADTRG.
Section 9 I/O Ports 9.3.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Bit Name Initial Value R/W Description 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W When each of the port 5 pins P57 to P50 functions as a general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Section 9 I/O Ports 9.3.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W 7, 6 All 0 Description Reserved These bits are always read as 0. 5 PUCR55 0 R/W 4 PUCR54 0 R/W 3 PUCR53 0 R/W 2 PUCR52 0 R/W 1 PUCR51 0 R/W 0 PUCR50 0 R/W 9.3.5 Pin Functions Only bits for which PCR5 is cleared are valid.
Section 9 I/O Ports • P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function Setting Value 0 0 P55 input pin 1 P55 output pin X WKP5/ADTRG input pin 1 [Legend] X: Don't care. • P54/WKP4 pin Register PMR5 PCR5 Bit Name WKP4 PCR54 Pin Function Setting Value 0 0 P54 input pin 1 P54 output pin X WKP4 input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports • P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Pin Function Setting Value 0 0 P52 input pin 1 P52 output pin X WKP2 input pin 1 [Legend] X: Don't care. • P51/WKP1 pin Register PMR5 PCR5 Bit Name WKP1 PCR51 Pin Function Setting Value 0 0 P51 input pin 1 P51 output pin X WKP1 input pin 1 [Legend] X: Don't care.
Section 9 I/O Ports 9.4 Port 6 Port 6 is a general I/O port also functioning as a timer Z I/O pin. Each pin of the port 6 is shown in figure 9.4. The register setting of the timer Z has priority for functions of the pins for both uses. P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 Port 6 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 Figure 9.4 Port 6 Pin Configuration Port 6 has the following registers. • Port control register 6 (PCR6) • Port data register 6 (PDR6) 9.4.
Section 9 I/O Ports 9.4.2 Port Data Register 6 (PDR6) PDR6 is a general I/O port data register of port 6. Bit Bit Name Initial Value R/W Description 7 P67 0 R/W Stores output data for port 6 pins. 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W If PDR6 is read while PCR6 bits are set to 1, the value stored in PDR6 are read. If PDR6 is read while PCR6 bits are cleared to 0, the pin states are read regardless of the value stored in PDR6.
Section 9 I/O Ports • P66/FTIOC1 pin Register TOER TFCR TPMR Bit Name EC1 CMD1, CMD0 IOC2 to PWMC1 IOC0 PCR66 Pin Function 00 0 0 P66 input/FTIOC1 input pin 1 P66 output pin X FTIOC1 output pin Setting Value 1 0 00 TIORC1 000 or 1XX 0 001 or 01X 1 XXX Other than X 00 XXX TIORA1 PCR6 [Legend] X: Don't care.
Section 9 I/O Ports • P64/FTIOA1 pin Register TOER TFCR TIORA1 PCR6 Bit Name EB1 CMD1, CMD0 IOA2 to IOA0 PCR64 Pin Function XX 000 or 0 P64 input/FTIOA1 input pin 1XX 1 P64 output pin 00 001 or 01X X FTIOA1 output pin TIORC0 PCR6 Setting Value 1 0 [Legend] X: Don't care.
Section 9 I/O Ports • P62/FTIOC0 pin Register TOER TFCR TPMR Bit Name EC0 CMD1, CMD0 IOC2 to PWMC0 IOC0 PCR62 Pin Function 00 0 0 P62 input/FTIOC0 input pin 1 P62 output pin X FTIOC0 output pin Setting Value 1 0 00 TIORC0 000 or 1XX 0 001 or 01X 1 XXX Other than X 00 XXX TIORA0 PCR6 [Legend] X: Don't care.
Section 9 I/O Ports • P60/FTIOA0 pin Register TOER TFCR TFCR TIORA0 PCR6 Bit Name EA0 CMD1, CMD0 STCLK IOA2 to IOA0 PCR60 Pin Function XX X 000 or 1XX 0 P60 input/FTIOA0 input pin 1 P60 output pin 001 or 01X X FTIOA0 output pin Setting Value 1 0 00 0 [Legend] X: Don't care. 9.5 Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin and SCI3_2 I/O pin. Each pin of the port 7 is shown in figure 9.5.
Section 9 I/O Ports 9.5.1 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Bit Bit Name Initial Value R/W Description 7 6 PCR76 0 W 5 PCR75 0 W When each of the port 7 pins P76 to P74 and P72 to P70 functions as a general I/O port, setting a PCR7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR74 0 W Bits 7 and 3 are reserved bits.
Section 9 I/O Ports 9.5.3 Pin Functions The correspondence between the register specification and the port functions is shown below. • P76/TMOV pin Register TCSRV Bit Name OS3 to OS0 PCR76 Pin Function Setting Value 0000 0 P76 input pin 1 P76 output pin X TMOV output pin Other than the above values PCR7 [Legend] X: Don't care.
Section 9 I/O Ports • P72/TXD_2* pin Register PMR1* PCR7 Bit Name TXD2* PCR72 Pin Function Setting Value 0 0 P72 input pin 1 P72 output pin X TXD_2 output pin* 1 [Legend] X: Don't care. Note: * The H8/36037 Group does not have this pin. • P71/RXD_2* pin Register SCR3_2* PCR7 Bit Name RE* PCR71 Pin Function Setting Value 0 0 P71 input pin 1 P71 output pin X RXD_2 input pin* 1 [Legend] X: Don't care. Note: * The H8/36037 Group does not have this pin.
Section 9 I/O Ports 9.6 Port 8 Port 8 is a general I/O port. Each pin of the port 8 is shown in figure 9.6. P87 Port 8 P86 P85 Figure 9.6 Port 8 Pin Configuration Port 8 has the following registers. • Port control register 8 (PCR8) • Port data register 8 (PDR8) 9.6.1 Port Control Register 8 (PCR8) PCR8 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 8.
Section 9 I/O Ports 9.6.2 Port Data Register 8 (PDR8) PDR8 is a general I/O port data register of port 8. Bit Bit Name Initial Value R/W Description 7 P87 0 R/W PDR8 stores output data for port 8 pins. 6 P86 0 R/W 5 P85 0 R/W If PDR8 is read while PCR8 bits are set to 1, the value stored in PDR8 is read. If PDR8 is read while PCR8 bits are cleared to 0, the pin states are read regardless of the value stored in PDR8. 4 to 0 All 1 Reserved These bits are always read as 1. 9.6.
Section 9 I/O Ports 9.7 Port 9 Port 9 is a general I/O port also functioning as a TinyCAN I/O pin and an SSU I/O pin. Each pin of the port 9 is shown in figure 9.7. P97/SSO P96/SSI P95/SSCK P94/SCS Port 9 P93 P92/HTXD P91/HRXD P90 Figure 9.7 Port 9 Pin Configuration Port 9 has the following registers. • Port control register 9 (PCR9) • Port data register 9 (PDR9) 9.7.1 Port Control Register 9 (PCR9) PCR9 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 9.
Section 9 I/O Ports 9.7.2 Port Data Register 9 (PDR9) PDR9 is a general I/O port data register of port 9. Bit Bit Name Initial Value R/W Description 7 P97 0 R/W Stores output data for port 9 pins. 6 P96 0 R/W 5 P95 0 R/W 4 P94 0 R/W If PDR9 is read while PCR9 bits are set to 1, the value stored in PDR9 are read. If PDR9 is read while PCR9 bits are cleared to 0, the pin states are read regardless of the value stored in PDR9.
Section 9 I/O Ports • P96/HRXD pin Register TCMR PCR9 Bit Name PMR96 PCR96 Pin Function Setting Value 0 0 P96 input pin 1 P96 output pin X HRXD output pin 1 [Legend] X: Don't care.
Section 9 I/O Ports • P92/SSO pin Register PCR9 Bit Name PCR92 Setting Value 0 Pin Function P92 input pin 1 P92 output pin X SSO input/SSO output pin [Legend] X: Don't care. Note: When this pin is used as the SSO pin, register settings of the SSU are required. For details, see section 16.4.4, Communication Modes and Pin Functions.
Section 9 I/O Ports 9.8 Port B Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.8. PB7/AN7 PB6/AN6 PB5/AN5 Port B PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 9.8 Port B Pin Configuration Port B has the following register. • Port data register B (PDRB) 9.8.1 Port Data Register B (PDRB) PDRB is a general input-only port data register of port B.
Section 9 I/O Ports Rev. 4.00 Mar.
Section 10 Timer B1 Section 10 Timer B1 The timer B1 is an 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 10.1 shows a block diagram of the timer B1. 10.1 Features • Selection of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/256, φ/64, φ/16, and φ/4) or an external clock (can be used to count external events). • An interrupt is generated when the counter overflows.
Section 10 Timer B1 10.2 Input/Output Pin Table 10.1 shows the timer B1 pin configuration. Table 10.1 Pin Configuration Name Abbreviation I/O Function Timer B1 event input TMIB1 Input Event input to TCB1 Rev. 4.00 Mar.
Section 10 Timer B1 10.3 Register Descriptions The timer B1 has the following registers. • Timer mode register B1 (TMB1) • Timer counter B1 (TCB1) • Timer load register B1 (TLB1) 10.3.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock. Bit Bit Name Initial Value R/W Description 7 TMB17 0 R/W Auto-reload function select 0: Interval timer function selected 1: Auto-reload function selected 6 to 3 All 1 Reserved These bits are always read as 1.
Section 10 Timer B1 10.3.2 Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 values can be read by the CPU at any time. When TCB1 overflows from H'FF to H'00 or to the value set in TLB1, the IRRTB1 flag in IRR2 is set to 1. TCB1 is allocated to the same address as TLB1. TCB1 is initialized to H'00. 10.3.
Section 10 Timer B1 10.4 Operation 10.4.1 Interval Timer Operation When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared to 0, so up-counting and interval timing resume immediately. The operating clock of the timer B1 is selected from seven internal clock signals output by prescaler S, or an external clock input at pin TMB1. The selection is made by bits TMB12 to TMB10 in TMB1.
Section 10 Timer B1 10.5 Timer B1 Operating Modes Table 10.2 shows the timer B1 operating modes. Table 10.2 Timer B1 Operating Modes Operating Mode Reset Active Sleep Subactive Subsleep Standby TCB1 Interval Reset Functions Functions Halted Halted Halted Reset Functions Functions Halted Halted Halted Reset Functions Retained Retained Retained Retained Autoreload TMB1 Rev. 4.00 Mar.
Section 11 Timer V Section 11 Timer V The timer V is an 8-bit timer based on an 8-bit counter. The timer V counts external events. Compare-match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 11.
Section 11 Timer V TCRV1 TCORB Trigger control TRGV Comparator TCNTV Internal data bus Clock select TMCIV Comparator φ PSS TCORA TMRIV Clear control TCRV0 Interrupt request control TMOV Output control TCSRV [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0 TCRV1: Timer control register V1 PSS: Prescaler S CMIA: Compare-match interrupt A CMIB: Compare-match interrupt B OVI: O
Section 11 Timer V 11.2 Input/Output Pins Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration Name Abbreviation I/O Function Timer V output TMOV Output Timer V waveform output Timer V clock input TMCIV Input Clock input to TCNTV Timer V reset input TMRIV Input External input to reset TCNTV Trigger input TRGV Input Trigger input to initiate counting 11.3 Register Descriptions The time V has the following registers.
Section 11 Timer V 11.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set to 1 in TCRV0, a CPU interrupt is requested. Note that they must not be compared during the T3 state of a TCORA write cycle.
Section 11 Timer V Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W These bits select clock signals to input to TCNTV and the counting condition in combination with ICKS0 in TCRV1. Refer to table 11.2. Table 11.
Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match.
Section 11 Timer V Bit Bit Name Initial Value R/W Description 1 OS1 0 R/W Output Select 1 and 0 0 OS0 0 R/W These bits select an output method for the TMOV pin by the compare match of TCORA and TCNTV. 00: No change 01: 0 output 10: 1 output 11: Output toggles OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match.
Section 11 Timer V Bit Bit Name Initial Value R/W Description 1 1 Reserved This bit is always read as 1. 0 ICKS0 0 R/W Internal Clock Select 0 This bit selects clock signals to input to TCNTV in combination with CKS2 to CKS0 in TCRV0. Refer to table 11.2. 11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals.
Section 11 Timer V φ Internal clock TCNTV input clock TCNTV N–1 N N+1 Figure 11.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock TCNTV N–1 N N+1 Figure 11.3 Increment Timing with External Clock φ TCNTV H'FF H'00 Overflow signal OVF Figure 11.4 OVF Set Timing Rev. 4.00 Mar.
Section 11 Timer V φ TCNTV N TCORA or TCORB N N+1 Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output pin Figure 11.6 TMOV Output Timing φ Compare match A signal TCNTV N H'00 Figure 11.7 Clear Timing by Compare Match Rev. 4.00 Mar.
Section 11 Timer V φ TMRIV (External counter reset pin) TCNTV reset signal N–1 TCNTV N H'00 Figure 11.8 Clear Timing by TMRIV Input 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2.
Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3.
Section 11 Timer V 11.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence. 2.
Section 11 Timer V TCORA write cycle by CPU T2 T1 T3 φ Address TCORA address Internal write signal TCNTV N N+1 TCORA N M TCORA write data Compare match signal Inhibited Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 11.13 Internal Clock Switching and TCNTV Operation Rev. 4.00 Mar.
Section 12 Timer Z Section 12 Timer Z The timer Z has a 16-bit timer with two channels. Figures 12.1, 12.2, and 12.3 show the block diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z functions, refer to table 12.1. 12.
Section 12 Timer Z • Eleven interrupt sources Four compare match/input capture interrupts and an overflow interrupt are available for each channel. An underflow interrupt can be set for channel 1. Table 12.
Section 12 Timer Z ITMZ0 FTIOA0 ITMZ1 FTIOB0 FTIOC0 FTIOD0 Control logic FTIOA1 FTIOB1 FTIOC1 FTIOD1 φ, φ/2, φ/4, φ/8 ADTRG Channel 0 timer Channel 1 timer TSTR TMDR TPMR TFCR TOER TOCR Module data bus [Legend] TSTR : Timer start register (8 bits) TMDR : Timer mode register (8 bits) TPMR : Timer PWM mode register (8 bits) TFCR : Timer function control register (8 bits) TOER : Timer output master enable register (8 bits) TOCR : Timer output control register (8 bits) ADTRG : A/D conversi
Section 12 Timer Z FTIOA0 FTIOB0 φ, φ/2, φ/4, φ/8 FTIOC0 Clock select FTIOD0 Control logic ITMZ0 Module data bus [Legend] TCNT_0 : GRA_0, GRB_0, GRC_0, GRD_0 : TCR_0 : TIORA_0 : TIORC_0 : TSR_0 : TIER_0 : POCR_0 : ITMZ0 : Timer counter_0 (16 bits) General registers A_0, B_0, C_0, and D_0 (input capture/output compare registers: 16 bits × 4) Timer control register_0 (8 bits) Timer I/O control register A_0 (8 bits) Timer I/O control register C_0 (8 bits) Timer status register_0 (8 bits) Timer interr
Section 12 Timer Z FTIOA1 FTIOB1 φ, φ/2, φ/4, φ/8 FTIOC1 Clock select FTIOD1 Control logic ITMZ1 POCR_1 TIER_1 TSR_1 TIORC_1 TIORA_1 TCR_1 GRD_1 GRC_1 GRB_1 GRA_1 TCNT_1 Comparator Module data bus [Legend] TCNT_1 : GRA_1, GRB_1, GRC_1, GRD_1 : TCR_1 : TIORA_1 : TIORC_1 : TSR_1 : TIER_1 : POCR_1 : ITMZ1 : Timer counter_1 (16 bits) General registers A_1, B_1, C_1, and D_1 (input capture/output compare registers: 16 bits × 4) Timer control register_1 (8 bits) Timer I/O control register A_
Section 12 Timer Z 12.2 Input/Output Pins Table 12.2 summarizes the timer Z pins. Table 12.
Section 12 Timer Z 12.3 Register Descriptions The timer Z has the following registers.
Section 12 Timer Z • General register C_1 (GRC_1) • General register D_1 (GRD_1) 12.3.1 Timer Start Register (TSTR) TSTR selects the operation/stop for the TCNT counter. Bit Bit Name Initial Value R/W Description 7 to 2 All 1 Reserved These bits are always read as 1 and cannot be modified. 1 STR1 0 R/W Channel 1 Counter Start 0: TCNT_1 halts counting 1: TCNT_1 starts counting 0 STR0 0 R/W Channel 0 Counter Start 0: TCNT_0 halts counting 1: TCNT_0 starts counting Rev. 4.00 Mar.
Section 12 Timer Z 12.3.2 Timer Mode Register (TMDR) TMDR selects buffer operation settings and synchronized operation.
Section 12 Timer Z 12.3.3 Timer PWM Mode Register (TPMR) TPMR sets the pin to enter PWM mode. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1 and cannot be modified.
Section 12 Timer Z 12.3.4 Timer Function Control Register (TFCR) TFCR selects the settings and output levels for each operating mode. Bit Bit Name Initial Value R/W Description 7 1 Reserved This bit is always read as 1.
Section 12 Timer Z Bit Bit Name Initial Value R/W Description 1 CMD1 0 R/W Combination Mode 1 and 0 0 CMD0 0 R/W 00: Channel 0 and channel 1 operate normally 01: Channel 0 and channel 1 are used together to operate in reset synchronous PWM mode 10: Channel 0 and channel 1 are used together to operate in complementary PWM mode (transferred at the trough) 11: Channel 0 and channel 1 are used together to operate in complementary PWM mode (transferred at the crest) Note: When reset synchronous PW
Section 12 Timer Z 12.3.5 Timer Output Master Enable Register (TOER) TOER enables/disables the outputs for channel 0 and channel 1. When WKP4 is selected for inputs, if a low level signal is input to WKP4, the bits in TOER are set to 1 to disable the output for timer Z.
Section 12 Timer Z Bit Bit Name Initial Value R/W Description 2 EC0 1 R/W Master Enable C0 0: FTIOC0 pin output is enabled according to the TPMR, TFCR, and TIORC_0 settings 1: FTIOC0 pin output is disabled regardless of the TPMR, TFCR, and TIORC_0 settings (FTIOC0 pin is operated as an I/O port).
Section 12 Timer Z Bit Bit Name Initial Value R/W Description 4 TOA1 0 R/W Output Level Select A1 0: 0 output at the FTIOA1 pin* 1: 1 output at the FTIOA1 pin* 3 TOD0 0 R/W Output Level Select D0 0: 0 output at the FTIOD0 pin* 1: 1 output at the FTIOD0 pin* 2 TOC0 0 R/W Output Level Select C0 0: 0 output at the FTIOC0 pin* 1: 1 output at the FTIOC0 pin* 1 TOB0 0 R/W Output Level Select B0 0: 0 output at the FTIOB0 pin* 1: 1 output at the FTIOB0 pin* 0 TOA0 0 R/W Output Level Se
Section 12 Timer Z 12.3.8 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD) GR are 16-bit registers. Timer Z has eight general registers (GR), four for each channel. The GR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. Functions can be switched by TIORA and TIORC. The values in GR and TCNT are constantly compared with each other when the GR registers are used as output compare registers.
Section 12 Timer Z 12.3.9 Timer Control Register (TCR) The TCR registers select a TCNT counter clock, an edge when an external clock is selected, and counter clearing sources. Timer Z has a total of two TCR registers, one for each channel.
Section 12 Timer Z 12.3.10 Timer I/O Control Register (TIORA and TIORC) The TIOR registers control the general registers (GR). Timer Z has four TIOR registers (TIORA_0, TIORA_1, TIORC_0, and TIORC_1), two for each channel. In PWM mode including complementary PWM mode and reset synchronous PWM mode, the settings of TIOR are invalid. TIORA: TIORA selects whether GRA or GRB is used as an output compare register or an input capture register.
Section 12 Timer Z Bit Bit Name Initial Value R/W Description 2 IOA2 0 R/W I/O Control A2 to A0 1 IOA1 0 R/W GRA is an output compare register: 0 IOA0 0 R/W 000: Disables pin output by compare match 001: 0 output by GRA compare match 010: 1 output by GRA compare match 011: Toggle output by GRA compare match GRA is an input capture register: 100: Input capture to GRA at the rising edge 101: Input capture to GRA at the falling edge 11X: Input capture to GRA at both rising and falling edges
Section 12 Timer Z Bit Bit Name Initial value R/W Description 2 IOC2 0 R/W I/O Control C2 to C0 1 IOC1 0 R/W GRC is an output compare register: 0 IOC0 0 R/W 000: Disables pin output by compare match 001: 0 output by GRC compare match 010: 1 output by GRC compare match 011: Toggle Output by GRC compare match GRC is an input capture register: 100: Input capture to GRC at the rising edge 101: Input capture to GRC at the falling edge 11X: Input capture to GRC at both rising and falling edges
Section 12 Timer Z Bit Bit Name Initial Value R/W Description 3 IMFD 0 R/W Input Capture/Compare Match Flag D [Setting conditions] • When TCNT = GRD and GRD is functioning as output compare register • When TCNT value is transferred to GRD by input capture signal and GRD is functioning as input capture register [Clearing condition] • 2 IMFC 0 R/W When 0 is written to IMFD after reading IMFD = 1 Input Capture/Compare Match Flag C [Setting conditions] • When TCNT = GRC and GRC is functionin
Section 12 Timer Z Bit Bit Name Initial Value R/W Description 0 IMFA 0 R/W Input Capture/Compare Match Flag A [Setting conditions] • When TCNT = GRA and GRA is functioning as output compare register • When TCNT value is transferred to GRA by input capture signal and GRA is functioning as input capture register [Clearing condition] • When 0 is written to IMFA after reading IMFA = 1 Note: Bit 5 is not the UDF flag in TSR_0. It is a reserved bit. It is always read as 1. 12.3.
Section 12 Timer Z Bit Bit Name Initial Value R/W Description 0 IMIEA 0 R/W Input Capture/Compare Match Interrupt Enable A 0: Interrupt requests (IMIA) by IMFA flag are disabled 1: Interrupt requests (IMIA) by IMFA flag are enabled 12.3.13 PWM Mode Output Level Control Register (POCR) POCR control the active level in PWM mode. Timer Z has two POCR registers, one for each channel.
Section 12 Timer Z 12.3.14 Interface with CPU 16-Bit Register: TCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be accessed in a 16-bit unit. Figure 12.5 shows an example of accessing the 16-bit registers. Internal data bus H C P L Module data bus Bus interface U TCNTH TCNTL Figure 12.
Section 12 Timer Z 12.4 Operation 12.4.1 Counter Operation When one of bits STR0 and STR1 in TSTR is set to 1, the TCNT counter for the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic counter, for example. Figure 12.7 shows an example of the counter operation setting procedure.
Section 12 Timer Z Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the TCNT counters for channels 0 and 1 are all designated as free-running counters. When the relevant bit in TSTR is set to 1, the corresponding TCNT counter starts an increment operation as a free-running counter. When TCNT overflows, the OVF flag in TSR is set to 1. If the value of the OVIE bit in the corresponding TIER is 1 at this point, timer Z requests an interrupt.
Section 12 Timer Z Figure 12.9 illustrates periodic counter operation. TCNT value Counter cleared by GR compare match GR value H'0000 Time STR IMF Figure 12.9 Periodic Counter Operation TCNT Count Timing: • Internal clock operation A system clock (φ) or three types of clocks (φ/2, φ/4, or φ/8) that divides the system clock can be selected by bits TPSC2 to TPSC0 in TCR. Figure 12.10 illustrates this timing. φ Internal clock TCNT input TCNT N-1 N N+1 Figure 12.
Section 12 Timer Z • External clock operation An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TCR, and a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the rising edge, falling edge, or both edges can be selected. The pulse width of the external clock needs two or more system clocks. Note that an external clock does not operate correctly with the lower pulse width. Figure 12.
Section 12 Timer Z 12.4.2 Waveform Output by Compare Match Timer Z can perform 0, 1, or toggle output from the corresponding FTIOA, FTIOB, FTIOC, or FTIOD output pin using compare match A, B, C, or D. Figure 12.12 shows an example of the setting procedure for waveform output by compare match.
Section 12 Timer Z Examples of Waveform Output Operation: Figure 12.13 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made such that 0 is output by compare match A, and 1 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF Time H'0000 FTIOB No change FTIOA No change No change No change Figure 12.
Section 12 Timer Z Figure 12.14 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing on compare match B), and settings have been made such that the output is toggled by both compare match A and compare match B. TCNT value GRB GRA Time H'0000 Toggle output FTIOB FTIOA Toggle output Figure 12.14 Example of Toggle Output Operation Rev. 4.00 Mar.
Section 12 Timer Z Output Compare Timing: The compare match signal is generated in the last state in which TCNT and GR match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD). When TCNT matches GR, the compare match signal is generated only after the next TCNT input clock pulse is input. Figure 12.
Section 12 Timer Z 12.4.3 Input Capture Function The TCNT value can be transferred to GR on detection of the input edge of the input capture/output compare pin (FTIOA, FTIOB, FTIOC, or FTIOD). Rising edge, falling edge, or both edges can be selected as the detected edge. When the input capture function is used, the pulse width or period can be measured. Figure 12.16 shows an example of the input capture operation setting procedure.
Section 12 Timer Z Example of Input Capture Operation: Figure 12.17 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the FTIOA pin input capture input edge, the falling edge has been selected as the FTIOB pin input capture input edge, and counter clearing by GRB input capture has been designated for TCNT.
Section 12 Timer Z Input Capture Signal Timing: Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR. Figure 12.18 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles. φ Input capture input Input capture signal TCNT N GR N Figure 12.18 Input Capture Signal Timing Rev. 4.00 Mar.
Section 12 Timer Z 12.4.4 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables GR to be increased with respect to a single time base. Figure 12.19 shows an example of the synchronous operation setting procedure.
Section 12 Timer Z Figure 12.20 shows an example of synchronous operation. In this example, synchronous operation has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. In addition, the same input clock has been set as the counter input clock for channel 0 and channel 1. Two-phase PWM waveforms are output from pins FTIOB0 and FTIOB1.
Section 12 Timer Z 12.4.5 PWM Mode In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD output pins with GRA as a cycle register and GRB, GRC, and GRD as duty registers. The initial output level of the corresponding pin depends on the setting values of TOCR and POCR. Table 12.3 shows an example of the initial output level of the FTIOB0 pin. The output level is determined by the POLB to POLD bits corresponding to POCR.
Section 12 Timer Z PWM mode Select counter clock [1] Select counter clearing source [2] Set PWM mode [3] Set initial output level [4] Select output level [5] Set GR [6] Enable waveform output [7] Start counter operation [8] [1] Select the counter clock with bits TPSC2 to TOSC0 in TCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR1 and CCLR0 in TCR to select the counter clearing source.
Section 12 Timer Z Figure 12.22 shows an example of operation in PWM mode. The output signals go to 1 and TCNT is reset at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0). Counter cleared by GRA compare match TCNT value GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 12.22 Example of PWM Mode Operation (1) Rev. 4.00 Mar.
Section 12 Timer Z Figure 12.23 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is reset at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1). Counter cleared by GRA compare match TCNT value GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 12.23 Example of PWM Mode Operation (2) Figures 12.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 12.
Section 12 Timer Z TCNT value GRB rewritten GRA GRB rewritten GRB Time H'0000 0% duty FTIOB TCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRA GRB rewritten GRB rewritten GRB H'0000 Time FTIOB 100% duty When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
Section 12 Timer Z TCNT value GRB rewritten GRA GRB rewritten GRB H'0000 Time FTIOB 0% duty TCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority. GRA GRB rewritten GRB rewritten GRB Time H'0000 100% duty FTIOB When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
Section 12 Timer Z 12.4.6 Reset Synchronous PWM Mode Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 performs an increment operation. Tables 12.4 and 12.5 show the PWM-output pins used and the register settings, respectively. Figure 12.
Section 12 Timer Z Reset synchronous PWM mode Stop counter operation [1] Select counter clock [2] Select counter clearing source [3] Set reset synchronous PWM mode [4] Initialize the output pin [5] Set TCNT [6] Set GR [7] Enable waveform output [8] Start counter operation [9] [1] Clear bit STR0 in TSTR to 0 and stop the counter operation of TCNT_0. Set reset synchronous PWM mode after TCNT_0 stops. [2] Select the counter clock with bits TPSC2 to TOSC0 in TCR.
Section 12 Timer Z Figures 12.27 and 12.28 show examples of operation in reset synchronous PWM mode. Counter cleared by GRA compare match TCNT value GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 12.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) Rev. 4.00 Mar.
Section 12 Timer Z Counter cleared by GRA compare match TCNT value GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 12.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) In reset synchronous PWM mode, TCNT_0 and TCNT_1 perform increment and independent operations, respectively. However, GRA_1 and GRB_1 are separated from TCNT_1.
Section 12 Timer Z 12.4.7 Complementary PWM Mode Three PWM waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TCNT_0 and TCNT_1 perform an increment or decrement operation. Tables 12.6 and 12.7 show the output pins and register settings in complementary PWM mode, respectively. Figure 12.
Section 12 Timer Z Table 12.7 Register Settings in Complementary PWM Mode Register Description TCNT_0 Initial setting of non-overlapped periods (non-overlapped periods are differences with TCNT_1) TCNT_1 Initial setting of H'0000 GRA_0 Sets (upper limit value – 1) of TCNT_0 GRB_0 Set a changing point of the PWM waveform output from pins FTIOB0 and FTIOD0. GRA_1 Set a changing point of the PWM waveform output from pins FTIOA1 and FTIOC1.
Section 12 Timer Z Complementary PWM mode Stop counter operation [1] Initialize output pin [2] Select counter clock [3] Set complementary PWM mode [4] Initialize output pin [5] Set TCNT [6] Set GR [7] Enable waveform output [8] Start counter operation [9] [1] Clear bits STR0 and STR1 in TSTR to 0, and stop the counter operation of TCNT_0. Stop TCNT_0 and TCNT_1 and set complementary PWM mode. [2] Write H'00 to TOCR.
Section 12 Timer Z Canceling Procedure of Complementary PWM Mode: Figure 12.30 shows the complementary PWM mode canceling procedure. Complementary PWM mode Stop counter operation [1] Cancel complementary PWM mode [2] [1] Clear bit CMD1 in TFCR to 0, and set channels 0 and 1 to normal operation. [2] After setting channels 0 and 1 to normal operation, clear bits STR0 and STR1 in TSTR to 0 and stop TCNT0 and TCNT1. Figure 12.30 Canceling Procedure of Complementary PWM Mode Rev. 4.
Section 12 Timer Z Examples of Complementary PWM Mode Operation: Figure 12.31 shows an example of complementary PWM mode operation. In complementary PWM mode, TCNT_0 and TCNT_1 perform an increment or decrement operation. When TCNT_0 and GRA_0 are compared and their contents match, the counter is decremented, and when TCNT_1 underflows, the counter is incremented.
Section 12 Timer Z Figure 12.32 (1) and (2) show examples of PWM waveform output with 0% duty and 100% duty in complementary PWM mode (for one phase). • TPSC2 = TPSC1 = TPSC0 = 0 Set GRB_0 to H'0000 or a value equal to or more than GRA_0, and the waveform with a duty cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation. For details on buffer operation, see section 12.4.8, Buffer Operation.
Section 12 Timer Z TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 0% duty (a) When duty is 0% TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 100% duty (b) When duty is 100% Figure 12.32 (1) Example of Complementary PWM Mode Operation (TPSC2 = TPSC1 = TPSC0 = 0) (2) Rev. 4.00 Mar.
Section 12 Timer Z TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 0% duty (a) When duty is 0% TCNT values GRA0 GRB0 H'0000 Time FTIOB0 FTIOD0 100% duty (b) When duty is 100% Figure 12.32 (2) Example of Complementary PWM Mode Operation (Other than TPSC2 = TPSC1 = TPSC0) (3) Rev. 4.00 Mar.
Section 12 Timer Z In complementary PWM mode, when the counter switches from up-counter to down-counter or vice versa, TCNT_0 and TCNT_1 overshoots or undershoots, respectively. In this case, the conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings are shown in figures 12.33 and 12.34.
Section 12 Timer Z When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been designated for BR, BR is transferred to GR when the counter is incremented by compare match A0 or when TCNT_1 is underflowed. If the φ or φ/2 clock is selected by TPSC2 to TPSC0 bits, the OVF flag is not set to 1 at the timing that the counter value changes from H'FFFF to H'0000.
Section 12 Timer Z • To output a 100%-duty cycle waveform, write H'0000 while previous GR value < TCNT_0 ≤ GRA_0. • To change duty cycles while a waveform with a duty cycle of 0% or 100% is being output, make sure the following procedure. • To change duty cycles while a 0%-duty cycle waveform is being output, write to GR while H'0000 ≤TCNT_1 < previous GR value. • To change duty cycles while a 100%-duty cycle waveform is being output, write to GR while previous GR value< TCNT_0 ≤ GRA_0.
Section 12 Timer Z 12.4.8 Buffer Operation Buffer operation differs depending on whether GR has been designated for an input capture register or an output compare register, or in reset synchronous PWM mode or complementary PWM mode. Table 12.8 shows the register combinations used in buffer operation. Table 12.
Section 12 Timer Z Complementary PWM Mode: When the counter switches from counting up to counting down or vice versa, the value of the buffer register is transferred to the general register. Here, the value of the buffer register is transferred to the general register in the following timing: 1. When TCNT_0 and GRA_0 are compared and their contents match 2. When TCNT_1 underflows Reset Synchronous PWM Mode: The value of the buffer register is transferred from compare match A0 to the general register.
Section 12 Timer Z Examples of Buffer Operation: Figure 12.38 shows an operation example in which GRA has been designated as an output compare register, and buffer operation has been designated for GRA and GRC. This is an example of TCNT operating as a periodic counter cleared by compare match B. Pins FTIOA and FTIOB are set for toggle output by compare match A and B.
Section 12 Timer Z φ n TCNT n+1 Compare match signal Buffer transfer signal N GRC n GRA N Figure 12.39 Example of Compare Match Timing for Buffer Operation Figure 12.40 shows an operation example in which GRA has been designated as an input capture register, and buffer operation has been designated for GRA and GRC. Counter clearing by input capture B has been set for TCNT, and falling edges have been selected as the FIOCB pin input capture input edge.
Section 12 Timer Z Counter is cleared by the input capture B TCNT value H'0180 H'0160 H'0005 H'0000 Time FTIOB FTIOA GRA H'0005 GRC H'0160 H'0005 GRB H'0160 H'0180 Input capture A Figure 12.40 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register) Rev. 4.00 Mar.
Section 12 Timer Z φ FTIO pin Input capture signal TCNT n n+1 N GRA M n n N GRC m M M n Figure 12.41 Input Capture Timing of Buffer Operation Rev. 4.00 Mar.
Section 12 Timer Z Figures 12.42 and 12.43 show the operation examples when buffer operation has been designated for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM waveform of 0% duty is created by using the buffer operation and performing GRD_0 ≥ GRA_0. Data is transferred from GRD_0 to GRB_0 according to the settings of CMD_0 and CMD_1 when TCNT_0 and GRA_0 are compared and their contents match or when TCNT_1 underflows.
Section 12 Timer Z GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values) TCNT values TCNT_0 GRA_0 TCNT_1 H'0999 H'0000 Time GRB_0 GRD_0 H'0999 GRB_0 H'0999 H'0000 H'0999 H'0000 H'0999 FTIOC0 FTIOD0 Figure 12.43 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 = CMD0 = 1) Rev. 4.00 Mar.
Section 12 Timer Z 12.4.9 Timer Z Output Timing The outputs of channels 0 and 1 can be disabled or inverted by the settings of TOER and TOCR and the external level. Output Disable/Enable Timing of Timer Z by TOER: Setting the master enable bit in TOER to 1 disables the output of timer Z. By setting the PCR and PDR of the corresponding I/O port beforehand, any value can be output. Figure 12.44 shows the timing to enable or disable the output of timer Z by TOER.
Section 12 Timer Z Output Disable Timing of Timer Z by External Trigger: When P54/WKP4 is set as a WKP4 input pin, and low level is input to WKP4, the master enable bit in TOER is set to 1 and the output of timer Z will be disabled. φ WKP4 TOER Timer Z output pin H'FF N Timer Z output I/O port Timer Z output I/O port Figure 12.
Section 12 Timer Z Output Inverse Timing by POCR: The output level can be inverted by inverting the POLD, POLC, and POLB bits in POCR in PWM mode. Figure 12.47 shows the timing. T1 T2 φ Address bus POCR address TFCR Timer Z output pin Inverted Figure 12.47 Example of Output Inverse Timing of Timer Z by Writing to POCR Rev. 4.00 Mar.
Section 12 Timer Z 12.5 Interrupts There are three kinds of timer Z interrupt sources; input capture/compare match, overflow, and underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while the corresponding interrupt enable bit is set to 1. 12.5.1 Status Flag Set Timing IMF Flag Set Timing: The IMF flag is set to 1 by the compare match signal that is generated when the GR matches with the TCNT.
Section 12 Timer Z IMF Flag Set Timing at Input Capture: When an input capture signal is generated, the IMF flag is set to 1 and the value of TCNT is simultaneously transferred to corresponding GR. Figure 12.49 shows the timing. φ Input capture signal IMF TCNT N GR N ITMZ Figure 12.49 IMF Flag Set Timing at Input Capture Overflow Flag (OVF) Set Timing: The overflow flag is set to 1 when the TCNT overflows. Figure 12.50 shows the timing.
Section 12 Timer Z 12.5.2 Status Flag Clearing Timing The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 12.51 shows the timing in this case. φ Address TSR address WTSR (internal write signal) IMF, OVF ITMZ Figure 12.51 Status Flag Clearing Timing Rev. 4.00 Mar.
Section 12 Timer Z 12.6 Usage Notes Contention between TCNT Write and Clear Operations: If a counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not performed. Figure 12.52 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) Counter clear signal TCNT N H'0000 Clearing has priority. Figure 12.52 Contention between TCNT Write and Clear Operations Rev. 4.00 Mar.
Section 12 Timer Z Contention between TCNT Write and Increment Operations: If incrementation is done in the T2 state of a TCNT write cycle, TCNT writing has priority. Figure 12.53 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) TCNT input clock TCNT M N TCNT write data Figure 12.53 Contention between TCNT Write and Increment Operations Rev. 4.00 Mar.
Section 12 Timer Z Contention between GR Write and Compare Match: If a compare match occurs in the T2 state of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure 12.54 shows the timing in this case. GR write cycle T1 T2 φ GR address WGR (internal write signal) TCNT N GR N N+1 M GR write data Compare match signal Disabled Figure 12.54 Contention between GR Write and Compare Match Rev. 4.00 Mar.
Section 12 Timer Z Contention between TCNT Write and Overflow/Underflow: If overflow/underflow occurs in the T2 state of a TCNT write cycle, TCNT write has priority without an increment operation. At this time, the OVF flag is set to 1. Figure 12.55 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address WTCNT (internal write signal) TCNT input clock Overflow signal TCNT H'FFFF M TCNT write data OVF Figure 12.55 Contention between TCNT Write and Overflow Rev. 4.00 Mar.
Section 12 Timer Z Contention between GR Read and Input Capture: If an input capture signal is generated in the T1 state of a GR read cycle, the data that is read will be transferred before input capture transfer. Figure 12.56 shows the timing in this case. GR read cycle T1 T2 φ GR address Internal read signal Input capture signal GR Internal data bus X M X Figure 12.56 Contention between GR Read and Input Capture Rev. 4.00 Mar.
Section 12 Timer Z Contention between Count Clearing and Increment Operations by Input Capture: If an input capture and increment signals are simultaneously generated, count clearing by the input capture operation has priority without an increment operation. The TCNT contents before clearing counter are transferred to GR. Figure 12.57 shows the timing in this case. φ Input capture signal Counter clear signal TCNT input clock TCNT N GR H'0000 N Clearing has priority. Figure 12.
Section 12 Timer Z Contention between GR Write and Input Capture: If an input capture signal is generated in the T2 state of a GR write cycle, the input capture operation has priority and the write to GR is not performed. Figure 12.58 shows the timing in this case. GR write cycle T1 T2 φ Address bus GR address WGR (internal write signal) Input capture signal TCNT GR N M GR write data Figure 12.
Section 12 Timer Z Note on Clearing TSR Flag: When a specific flag in TSR is cleared, a combination of the BCLR or MOV instructions is used to read 1 from the flag and then write 0 to the flag. However, if another bit is set during this processing, the bit may also be cleared simultaneously. To avoid this, the following processing that does not use the BCLR instruction must be executed. Note that this note is only applied to the F-ZTAT version. This problem has already been solved in the mask ROM version.
Section 12 Timer Z TOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B0. When BCLR#2, @TOCR is executed to clear the TOC0 bit (the FTIOC0 signal is low) and compare match B0 occurs at the same timing as shown below, the H'02 writing to TOCR has priority and compare match B0 does not drive the FTIOB0 signal low; the FTIOB0 signal remains high.
Section 12 Timer Z Rev. 4.00 Mar.
Section 13 Watchdog Timer Section 13 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 13.1.
Section 13 Watchdog Timer 13.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 13.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction.
Section 13 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 WDON 0 R/W Watchdog Timer On TCWD starts counting up when WDON is set to 1 and halts when WDON is cleared to 0.
Section 13 Watchdog Timer 13.2.2 Timer Counter WD (TCWD) TCWD is an 8-bit readable/writable up-counter. When TCWD overflows from H'FF to H'00, the internal reset signal is generated and the WRST bit in TCSRWD is set to 1. TCWD is initialized to H'00. 13.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit Bit Name Initial Value R/W 7 CKS7 1 R/W Description Clock Select 7 Selects the subtimer internal oscillator.
Section 13 Watchdog Timer 13.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 256 φosc clock cycles.
Section 13 Watchdog Timer Rev. 4.00 Mar.
Section 14 Serial Communication Interface 3 (SCI3) Section 14 Serial Communication Interface 3 (SCI3) This LSI includes a serial communication interface 3 (SCI3), which has two independent channels*1. The SCI3 can handle both asynchronous and clocked synchronous serial communication.
Section 14 Serial Communication Interface 3 (SCI3) • Break detection: Break can be detected by reading the RXD pin level directly in the case of a framing error Clocked synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors Table 14.
Section 14 Serial Communication Interface 3 (SCI3) SCK3 External clock Internal clock (φ/64, φ/16, φ/4, φ) Baud rate generator BRC BRR Clock Transmit/receive control circuit Internal data bus SMR SCR3 SSR TXD TSR TDR RXD RSR RDR Interrupt request (TEI, TXI, RXI, ERI) [Legend] Receive shift register RSR: Receive data register RDR: Transmit shift register TSR: Transmit data register TDR: Serial mode register SMR: SCR3: Serial control register 3 Serial status register SSR: Bit rate register BRR
Section 14 Serial Communication Interface 3 (SCI3) 14.2 Input/Output Pins Table 14.2 shows the SCI3 pin configuration. Table 14.2 Pin Configuration Pin Name Abbreviation I/O Function SCI3 clock SCK3 I/O SCI3 clock input/output SCI3 receive data input RXD Input SCI3 receive data input SCI3 transmit data output TXD Output SCI3 transmit data output 14.3 Register Descriptions The SCI3 has the following registers for each channel.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 14.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.5 Serial Mode Register (SMR) SMR is used to set the SCI3’s serial transfer format and select the baud rate generator clock source. Bit Bit Name Initial Value R/W Description 7 COM 0 R/W Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/14 clock (n = 2) 11: φ/64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 14.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 14.3.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/W Transmit Data Register Empty Indicates whether TDR contains transmit data.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 PER 0 R/W Parity Error [Setting condition] • When a parity error is detected during reception [Clearing condition] • 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End [Setting conditions] • When the TE bit in SCR3 is 0 • When TDRE = 1 at transmission of the last bit of a 1frame serial transmit character [Clearing conditions] 1 MPBR 0 R • When 0 is written to TDRE af
Section 14 Serial Communication Interface 3 (SCI3) 14.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.3 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 14.4 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 14.3 and 14.4 are values in active (highspeed) mode. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 2 2.097152 2.4576 3 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.14 1 108 0.21 1 127 0.00 1 155 0.14 300 0 207 0.14 0 217 0.21 0 255 0.00 1 77 0.14 600 0 103 0.14 0 108 0.21 0 127 0.
Section 14 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 3.6864 4 4.9152 5 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.14 1 255 0.00 2 64 0.14 300 1 95 0.00 1 103 0.14 1 127 0.00 1 129 0.14 600 0 191 0.00 0 207 0.14 0 255 0.00 1 64 0.14 1200 0 95 0.00 0 103 0.14 0 127 0.00 0 129 0.14 2400 0 47 0.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6 6.144 7.3728 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 150 2 77 0.14 2 79 0.00 2 95 0.00 300 1 155 0.14 1 159 0.00 1 191 0.00 600 1 77 0.14 1 79 0.00 1 95 0.00 1200 0 155 0.14 0 159 0.00 0 191 0.00 2400 0 77 0.14 0 79 0.
Section 14 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 8 9.8304 10 12 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 141 0.03 2 174 –0.26 2 177 –0.25 2 212 0.03 150 2 103 0.14 2 127 0.00 2 129 0.14 2 155 0.14 300 1 207 0.14 1 255 0.00 2 64 0.14 2 77 0.14 600 1 103 0.14 1 127 0.00 1 129 0.14 1 155 0.14 1200 0 207 0.14 0 255 0.00 1 64 0.14 1 77 0.14 2400 0 103 0.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ (MHz) 12.888 14 14.7456 14 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 217 0.08 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 159 0.00 2 181 0.14 2 191 0.00 2 207 0.14 300 2 79 0.00 2 90 0.14 2 95 0.00 2 103 0.14 600 1 159 0.00 1 181 0.14 1 191 0.00 1 207 0.
Section 14 Serial Communication Interface 3 (SCI3) Operating Frequency φ (MHz) 18 20 Bit Rate (bit/s) n N Error (%) n N Error (%) 110 3 79 –0.12 3 88 –0.25 150 2 233 0.14 3 64 0.14 300 2 114 0.14 2 129 0.14 600 1 233 0.14 2 64 0.14 1200 1 114 0.14 1 129 0.14 2400 0 233 0.14 1 64 0.14 4800 0 114 0.14 0 129 0.14 9600 0 58 –0.96 0 64 0.14 19200 0 28 1.02 0 32 –1.36 31250 0 17 0.00 0 19 0.00 38400 0 14 –2.34 0 15 1.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (1) Operating Frequency φ (MHz) 2 4 8 10 Bit Rate (bit/s) n N n N n N n N 110 3 70 — — — — — — 250 2 124 2 249 3 124 — — 16 n N 3 249 500 1 249 2 124 2 249 — — 3 124 1k 1 124 1 249 2 124 — — 2 249 2.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) Operating Frequency φ (MHz) 18 20 Bit Rate (bit/s) n N n N 110 — — — — 250 — — — — 500 3 140 3 155 1k 3 69 3 77 2.5k 2 112 2 124 5k 1 224 1 249 10k 1 112 1 124 25k 0 179 0 199 50k 0 89 0 99 100k 0 44 0 49 250k 0 17 0 19 500k 0 8 0 9 1M 0 4 0 4 2M — — — — 2.
Section 14 Serial Communication Interface 3 (SCI3) 14.4 Operation in Asynchronous Mode Figure 14.2 shows the general format for asynchronous serial communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.2 SCI3 Initialization Before transmitting and receiving data, you should first clear the TE and RE bits in SCR3 to 0, then initialize the SCI3 as described below. When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.3 Data Transmission Figure 14.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR [2] Yes All data transmitted? [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.4 Serial Data Reception Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.6 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.8 shows a sample flow chart for serial data reception. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR [2] No RDRF = 1 Yes Read receive data in RDR [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically.
Section 14 Serial Communication Interface 3 (SCI3) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 14.8 Sample Serial Reception Data Flowchart (Asynchronous Mode) (2) Rev. 4.00 Mar.
Section 14 Serial Communication Interface 3 (SCI3) 14.5 Operation in Clocked Synchronous Mode Figure 14.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the synchronization clock to the next.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.3 Serial Data Transmission Figure 14.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 Yes [2] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronization clock input or output, starts receiving data. 2. The SCI3 stores the receive data in RSR. 3.
Section 14 Serial Communication Interface 3 (SCI3) Start reception [1] [1] Read OER flag in SSR [2] Yes OER = 1 [4] No Error processing [3] (Continued below) Read RDRF flag in SSR [2] [4] No RDRF = 1 Yes Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.5 Simultaneous Serial Data Transmission and Reception Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission/reception Read TDRE flag in SSR [1] [1] No TDRE = 1 Yes Write transmit data to TDR Read OER flag in SSR OER = 1 No Read RDRF flag in SSR Yes [4] Error processing [2] No RDRF = 1 Yes Read receive data in RDR Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
Section 14 Serial Communication Interface 3 (SCI3) 14.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Section 14 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 14.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 [2] Yes Set MPBT bit in SSR [3] Write transmit data to TDR Yes [2] Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 14 Serial Communication Interface 3 (SCI3) generated at this time. All other SCI3 operations are the same as those in asynchronous mode. Figure 14.18 shows an example of SCI3 operation for multiprocessor format reception.
Section 14 Serial Communication Interface 3 (SCI3) [5] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No [A] Framing error processing Clear OER, and FER flags in SSR to 0 Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 4.00 Mar.
Section 14 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 User processing RXI interrupt request is not generated, and RDR retains its state RDR data read When data is not this station's ID, MPIE is set to 1 again (a
Section 14 Serial Communication Interface 3 (SCI3) 14.7 Interrupts The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.7 shows the interrupt sources. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) 14.8 Usage Notes 14.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RXD pin value directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 14.8.
Section 14 Serial Communication Interface 3 (SCI3) 14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 14 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 14.19.
Section 14 Serial Communication Interface 3 (SCI3) Rev. 4.00 Mar.
Section 15 Controller Area Network for Tiny (TinyCAN) Section 15 Controller Area Network for Tiny (TinyCAN) The TinyCAN is a module for controlling a controller area network (CAN) for realtime communication in vehicular and industrial equipment systems, etc and conforms to the Bosch 2.0B active. For details on CAN specifications, refer to Bosch CAN Specification Version 2.0 1991, Robert Bosch GmbH. 15.1 Features • CAN version: Conforms to Bosch 2.
Section 15 Controller Area Network for Tiny (TinyCAN) • Other features Standby mode can be cleared by falling edge detection of the HRXD pin. The block diagram of the TinyCAN is shown in figure 15.1.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.2 Input/Output Pins Table 15.1 shows the TinyCAN pin configuration. TinyCAN pins must be configured in configuration mode (while the RSTRQ bit in MCR and the RESET bit in GSR are both set to 1). A bus driver is necessary for the interface between the TinyCAN pins and the CAN bus. A Renesas Technology HA13721 compatible model is recommended. Table 15.
Section 15 Controller Area Network for Tiny (TinyCAN) • Message control (MCn0, MCn4 to MCn7 [n = 0 to 3]) • Local acceptance filter mask (LAFMHn1, LAFMHn0, LAFMLn1, and LAFMLn0 [n = 0 to 3]) • Message data (MDn0 to MDn7 [n = 0 to 3]) 15.3.1 Test Control Register (TCR) TCR controls the CDLC test mode. TCR must be configured in the initial state or in halt mode. For details, see section 15.7, Test Mode Settings.
Section 15 Controller Area Network for Tiny (TinyCAN) Bit Bit Name Initial Value R/W Description 3 DEC 0 R/W Error Count Disable Bit Enables or disables the TEC and REC to be functional. 0: TEC and REC function according to CAN specification 1: TEC and REC is disabled to function (count value is retained, enabled only in test mode) 2 DRXIN 0 R/W HRXD Pin Input Enable Enables or disables the HRXD pin to be supplied into the CDLC.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.2 Master Control Register (MCR) MCR controls a transition request to halt mode and a software reset request. Bit Bit Name Initial Value R/W Description 7 to 2 — All 0 R/W Reserved These bits are always read as 0. 1 HLTRQ 0 R/W Halt Request Halts communication between the TinyCAN and CAN bus. Communication with the CAN bus can be resumed by clearing this bit to 0 and then receiving 11 recessive bits.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.3 TinyCAN Module Control Register (TCMR) TCMR controls the configuration of module standby mode for the TinyCAN and selection of the P97/HTXD and P96/HRXD pins. Bit Bit Name Initial Value R/W Description 7 MSTTC 0 R/W TinyCAN Module Standby Control Bit Controls the configuration of module standby mode for the TinyCAN. When this bit is set to 1, the TinyCAN makes a transition to module standby mode.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.4 General Status Register (GSR) GSR indicates the status of the CAN bus. Each bit in GSR is set or cleared to notify the CPU of the TinyCAN status. Bit Bit Name Initial Value R/W Description 7, 6 — All 0 — Reserved 5 ERPS 0 R These bits are always read as 0. Error Passive Status Flag Indicates whether the CDLC is in the error-passive state. This flag is always set to 1 when the CDLC is in the errorpassive state or bus off state.
Section 15 Controller Area Network for Tiny (TinyCAN) Bit Bit Name Initial Value R/W Description 2 TCMPL 1 R Message Transmission Complete Flag Indicates whether the TinyCAN has finished message transmission. [Setting condition] When the TinyCAN has finished message transmission [Clearing condition] While a message is being transmitted (period from SOF (start of frame) to the third bit of the intermission space) 1 ECWRG 0 R Error Counter Warning Flag Indicates an error warning.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.5 Bit Configuration Registers 0, 1 (BCR0, BCR1) BCR configures the CAN bit timing parameters and baud rate prescaler for the CDLC. • BCR0 Bit Bit Name Initial Value R/W Description 7 SJW1 0 R/W Re-Synchronization Jump Width 6 SJW0 0 R/W These bits set the maximum value of synchronization width.
Section 15 Controller Area Network for Tiny (TinyCAN) Bit Bit Name Initial Value R/W Description 6 TSG22 0 R/W Time Segment 2 5 TSG21 0 R/W 4 TSG20 0 R/W This segment is used for correcting the error of 1 bit time. The TSG2 width can be set within a range of 2 to 8 time quanta.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.6 Mailbox Configuration Register (MBCR) MBCR configures each Mailbox as either reception or transmission, except for the receive-only Mailbox. Changing the corresponding bits for the receive-only Mailbox is ignored. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 — Reserved 3 MB3 0 R/W 2 MB2 0 R/W These bits are configured for the corresponding Mailboxes.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.7 Transmit Pending Register (TXPR) TXPR sets transmit pending (CAN bus arbitration wait) for the transmit message that is stored in a Mailbox. Setting the corresponding bit in TXPR to 1 enables a message to be transmitted. Writing 0 to the bit in TXPR is ignored. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 — Reserved These bits are always read as 0.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.8 Transmit Pending Cancel Register (TXCR) TXCR cancels transmission of transmit pending messages in Mailboxes. By setting the TXCR bit correspondent to TXPR, TXPR is cleared to 0. If the transmission has been canceled successfully, the corresponding bits in both TXPR and TXCR are cleared to 0 and then the corresponding bit in ABACK is set. Writing 0 to the bit in TXCR is ignored.
Section 15 Controller Area Network for Tiny (TinyCAN) Bit Bit Name Initial Value R/W 0 — 0 — Description Reserved This bit is always read as 0. This bit is relevant to the receive-only Mailbox, and its value cannot be changed. Note: * Only 1 can be written to clear the flag. 15.3.10 Abort Acknowledge Register (ABACK) ABACK is a status flag that indicates successful cancellation of Mailbox transmit messages.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.11 Data Frame Receive Complete Register (RXPR) RXPR is a status flag that indicates the successful reception of data frame messages in the corresponding Mailboxes. When the received data frame is successfully stored in the receive Mailbox, the corresponding RXPR bit is set to 1. When a remote frame is received, the bit is not set to 1. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 — Reserved These bits are always read as 0.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.13 Unread Message Status Register (UMSR) UMSR is a status flag that indicates that an unread message in each Mailbox has been overwritten by a new receive message or a new receive message has been discarded. Bit Bit Name Initial Value R/W Description 7 to 4 — All 0 — Reserved 3 MB3 0 2 MB2 0 R/(W)* Status flags indicating that a new receive message has R/(W)* overwritten/overrun an unread message.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.14 TinyCAN Interrupt Registers 0, 1 (TCIRR0, TCIRR1) TCIRR is a status flag for each interrupt source. • TCIRR0 Bit Bit Name Initial Value R/W 7 OVLI 0 R/(W)* Overload Frame Transmit Interrupt Flag Description Status flag indicating that the TinyCAN has transmitted an overload frame.
Section 15 Controller Area Network for Tiny (TinyCAN) Bit Bit Name Initial Value R/W 3 TOWI 0 R/(W)* Transmit Overload Warning Interrupt Flag Description Status flag indicating the error warning state caused by TEC. [Setting condition] When TEC ≥ 96 [Clearing condition] When 1 is written to this bit 2 RFRI 0 R Remote Frame Request Interrupt Flag Status flag indicating that a remote frame has been received in a Mailbox.
Section 15 Controller Area Network for Tiny (TinyCAN) • TCIRR1 Bit Bit Name Initial Value R/W Description 7 to 5 — All 0 — Reserved 4 WUPI 0 R/(W)* Wakeup Interrupt Flag These bits are always read as 0. Status flag indicating detection of a dominant bit on the CAN bus while the LSI is in standby mode. This flag can be set to 1 only in standby mode.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.15 Mailbox Interrupt Mask Register (MBIMR) MBIMR controls enabling or disabling of individual Mailbox interrupt requests. Setting and clearing each status flag has nothing to do with the configuration of bits in MBIMR. Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 — Reserved 3 MB3 1 R/W 2 MB2 1 R/W 1 MB1 1 R/W 0 MB0 1 R/W These bits are always read as 1.
Section 15 Controller Area Network for Tiny (TinyCAN) Bit Bit Name Initial Value R/W Description 6 BOFIM 1 R/W Bus Off Interrupt Mask Enables or disables a bus-off interrupt request. 0: The bus-off interrupt request is enabled 1: The bus-off interrupt request is disabled 5 EPIM 1 R/W Error Passive Interrupt Mask Enables or disables an error passive interrupt request.
Section 15 Controller Area Network for Tiny (TinyCAN) Bit Bit Name Initial Value R/W Description 0 RHIM 1 R/W Reset/Halt Interrupt Mask Enables or disables a reset/halt interrupt request. 0: The reset/halt interrupt request is enabled 1: The reset/halt interrupt request is disabled • TCIMR1 Bit Bit Name Initial Value R/W 7 to 5 — All 1 — Description Reserved These bits are always read as 1. 4 WUPIM 1 R/W Wakeup Interrupt Mask Enables or disables a wakeup interrupt request.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.3.17 Transmit Error Counter (TEC) TEC counts the number of transmit message errors on the CAN bus. Bit Bit Name Initial Value R/W Description 7 TEC7 0 R/W* 6 TEC6 0 R/W* 5 TEC5 0 R/W* 4 TEC4 0 R/W* 3 TEC3 0 R/W* TEC functions as a counter indicating the number of transmit message errors on the CAN bus. The count value is stipulated in the CAN protocol.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.4 Message Data and Control Each Mailbox has a storage area for control information and transmitted or received. 15.4.1 Message Control (MCn0, MCn4 to MCn7 [n = 0 to 3]) The message control configures the arbitration field and control field of the data frames and remote frames. The bit names in MCn0 and MCn4 to MCn7 correspond to the bit names of each frame.
Section 15 Controller Area Network for Tiny (TinyCAN) Register Name MCn[0] (n = 0 to 3) Bit Bit Name R/W Description 7 DART R/W Automatic Retransmission Disable When this bit is set to 1,the message disables to be retransmitted in the event of an error on CAN bus or an arbitration lost on CAN bus.
Section 15 Controller Area Network for Tiny (TinyCAN) Register Name MCn[4] (n = 0 to 3) Bit Bit Name R/W Description 4 RTR R/W Remote Transmission Request Distinguishes between data frame and remote frame. 0: Data frame 1: Remote frame 3 IDE R/W Identifier Extension Distinguishes between standard format and extended format. 0: Standard format 1: Extended format 2 — — Reserved This bit is always read as 0.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.4.2 Local Acceptance Filter Mask (LAFMHn1, LAFMHn0, LAFMLn1, LAFMLn0 [n = 0 to 3]) LAFM consists of four registers for one Mailbox. LAFM filters mask of bit-unit comparison between the message identifier of RXn (n = 0 to 3) stored in the receive Mailbox and the receive message identifier. Since LAFM is in RAM, initial values are undefined after power-on. Be sure to initialize each bit by writing 0 or 1.
Section 15 Controller Area Network for Tiny (TinyCAN) Register Name LAFMHn1 (n = 0 to 3) Bit Bit Name R/W Description 4 to 2 — — Reserved These bits are always read as 0. 1, 0 LAFMHn1, LAFMHn0 R/W Filter mask for bits 17 and 16 of the extended identifier.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.5 Operation 15.5.1 TinyCAN Initial Settings Figure 15.4 shows a flowchart for reset clearing of the TinyCAN. After a reset is cleared, all registers are initialized.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.5.2 Bit Timing The bit rate and bit timing are set by the bit configuration register (BCR). The CAN controllers connected to the CAN bus should be set so that all of them have the same baud rate and same bit width. One bit time consists of total settable Time Quantum (TQ).
Section 15 Controller Area Network for Tiny (TinyCAN) Time Quantum (TQ) is an integer multiple of the number of system clocks, and is determined by the baud rate prescaler (BRP) as follows. φ means the system clock frequency. TQ = (BRP + 1)/φ The following formula is used to calculate the 1-bit time and bit rate. 1-bit time = TQ × {1 + (1 + TSG1) + (1 + TSG2)} Bit rate = 1/Bit time = φ/{(BRP + 1) × {1 + (1 + TSG1) + (1 + TSG2)}} Values that can be set for TSG1 and TSG2 in BCR1 are listed in table 15.3.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.5.3 Message Transmission Message Transmission Request: Figure 15.6 shows a transmission flowchart.
Section 15 Controller Area Network for Tiny (TinyCAN) Internal Arbitration at Transmission: The TinyCAN transmits untransmitted messages in the priority order from Mailbox 3 to Mailbox 1. The internal arbitration function selects the Mailbox with the highest priority among all transmission request messages. Internal arbitration is based on the three sources given below. • TXPR/TXCR is set • Arbitration lost during message transmission • CAN bus error TXPR/TXCR Setting: Figure 15.
Section 15 Controller Area Network for Tiny (TinyCAN) Message 1 HRXD Bus idle HTXD Bus idle SOF Arbitration Control Data Message 2 CRC ACK EOF Intermission Message 1 SOF Arbitration Control Data SOF Message 2 CRC ACK EOF Intermission MBn in TXPR [4] Clear MBn in TXPR and MBn in TXCR MBn in TXCR MBn in TXACK [4] Set MBn in TXACK and EMPI in TCIRR1 EMPI in TCIRR1 MBn in ABACK Transmission for message 1 cannot be cancelled by TXCR Internal arbitration for message 2 can be configurable (T
Section 15 Controller Area Network for Tiny (TinyCAN) 4. If an arbitration loss occurs in the arbitration field, the TinyCAN starts reception. When the DART or MBn bit in TXCR is set to 1, a transmit request for message 1 is canceled. At this time, the MBn bits in TXPR and TXCR are cleared to 0 and the MBn bit in ABACK and the EMPI bit in TCIRR1 are set to 1. The MBn bit in TXACK is always 0. 5. When there is a transmit request after reception has completed (for details, see section 15.5.
Section 15 Controller Area Network for Tiny (TinyCAN) Message 1 Message 2 Bus idle HRXD SOF Arbitration Control Data CRC ACK EOF Intermission [4] Arbitration loss Bus idle HTXD SOF Arbitration SOF Message 2 ACK bit MBn in TXPR [4] Clear MBn in TXPR and MBn in TXCR for message 1 MBn in TXCR DART MBn in ABACK [4] Set MBn in ABACK and EMPI in TCIRR1 for message 1 EMPI in TCIRR1 MBn in TXACK Transmission for message 1 cannot be cancelled by TXCR Message 1 reception Internal arbitration f
Section 15 Controller Area Network for Tiny (TinyCAN) Message 1 HRXD Bus idle SOF Arbitration Control Data Message 2 CRC ACK EOF Intermission SOF [4] Arbitration loss HTXD Bus idle SOF Arbitration ACK Bit TXPR.MBn [4] Clear MBn bit in TXPR for message 1 TXCR.MBn [5] Overwrite DART bit for message 2 DART ABACK.MBn [4] Set MBn in ABACK and EMPI in TCIRR1 for message 1 TCIRR.EMPI TXACK.
Section 15 Controller Area Network for Tiny (TinyCAN) 4. If an arbitrary controller detects an error in a bit of the transmit message, the controller transmits an error frame. At this time, when the DART or MBn bit in TXCR of the TinyCAN is set to 1, a transmit request for message 1 is canceled. At the same time, the MBn bits in TXPR and TXCR are cleared to 0 and the MBn bit in ABACK and the EMPI bit in TCIRR1 are set to 1. The MBn bit in TXACK is always 0. 5.
Section 15 Controller Area Network for Tiny (TinyCAN) [4] Error frame detection Message 1 Bus idle HRXD SOF ..... Message 1 Bus idle HTXD SOF .....
Section 15 Controller Area Network for Tiny (TinyCAN) Message 1 Bus idle HRXD SOF ..... Message 1 HTXD Bus idle SOF ..... [4] Error frame detection Error Flag Error Flag Delimiter Message 2 Intermission [4] Error frame detection Error Flag SOF Message 2 Error Flag Delimiter [4] Clear MBn in TXPR TXPR.MBn TXCR.MBn [5] Overwrite DART when other Mailbox has transmit request DART ABACK.MBn [4] Set MBn in ABACK and EMPI in TCIRR1 TCIRR.EMPI TXACK.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.5.4 Message Reception Figure 15.14 shows a message reception flowchart. Figure 15.15 shows the set timing for TXPR and TXCR during reception. A transmit request can be canceled by TXCR at any time during reception.
Section 15 Controller Area Network for Tiny (TinyCAN) Receive procedure and operation are as follows. 1. Write data of a receive message to MCn0, MCn4 to MCn7, and MDn0 to MDn7 [n = 0 to 3] before setting MBCR corresponding to the Mailbox of the receive message to 1 (initial setting). 2. On detecting EOF of a data frame or remote frame, the TinyCAN compares the receive message identifier with the identifier set in the receive Mailbox.
Section 15 Controller Area Network for Tiny (TinyCAN) Message 1 HRXD Bus idle HTXD Bus idle SOF Arbitration Control Data Message 2 CRC ACK EOF Intermission SOF Message 2 ACK bit Intermission SOF [4] Clear MBn in TXCR to 0 even if set to 1 at frame reception MBn in TXPR MBn in TXCR [4] Set MBn in RXPR and DFRI in TCIRR0 to 1 at data frame reception MBn in RXPR DFRI in TCIRR0 [4] Set MBn in RFPR and RFRI in TCIRR0 to 1 at remote frame reception MBn in RFPR RFRI in TCIRR0 [2] Identifier
Section 15 Controller Area Network for Tiny (TinyCAN) Case 1: Overwrite (NMC = 1, 1st: Data Frame, 2nd: Remote Frame) Data frame reception Remote frame reception MBn in RXPR DFRI in TCIRR0 MBn in RFPR RFRI in TCIRR0 MBn in UMSR OVRI in TCIRR1 RTR in MCn4 CPU access Other module TinyCAN Case 2: Overwrite (NMC = 1, 1st: Remote Frame, 2nd: Data Frame) Remote frame reception Data frame reception MBn in RXPR DFRI in TCIRR0 MBn in RFPR RFRI in TCIRR0 MBn in UMSR OVRI in TCIRR1 RTR in MCn4 CPU access Othe
Section 15 Controller Area Network for Tiny (TinyCAN) 15.5.5 Reconfiguring Mailbox A Mailbox can be reconfigured using the following procedure: Changing CAN-ID and MBCR of Transmit Mailbox: Make sure that the bit corresponding to the Mailbox in TXPR is not set to 1. The identifier of the transmit Mailbox and corresponding MBCR bit can be changed at any time. If both of them need to be changed, change the identifier first, clear RXPR and RFPR to 0, and then change MBCR.
Section 15 Controller Area Network for Tiny (TinyCAN) Method 1: Halt mode Method 2: Other than halt mode TinyCAN is in normal mode TinyCAN is in normal mode Set HLTRQ in MCR to 1 (halt mode) TinyCAN is during transmission, reception, or in bus off state? No Set corresponding MBn in MBIMR to 1 Yes Read corresponding RXPR (RFPR) = 0 No Write 1 to MBn in RXPR (MBn in RFPR) Yes Interrupt occurred (RHI in TCIRR0 = 1) Change ID and MBCR of Mailbox Read RHI in TCIRR0 = 1 Read HALT in GSR = 1 Read
Section 15 Controller Area Network for Tiny (TinyCAN) 15.5.6 TinyCAN Standby Transition To make this LSI enter or clear standby mode when the TinyCAN is used or to make the TinyCAN enter or clear module standby mode, follow the procedure below. Transition from Normal Operation to Standby Mode or Module Standby Mode: This LSI can make a transition from normal mode to standby mode with the following procedure. 1. 2. 3. 4. Set the halt mode request bit (HLTRQ bit in MCR) to 1.
Section 15 Controller Area Network for Tiny (TinyCAN) Normal operation → LSI standby mode or Normal operation → module standby mode TinyCAN is in normal mode LSI standby mode → normal operation Module standby mode → normal operation TinyCAN is in module standby mode LSI standby mode Write 1 to HLTRQ in MCR (halt mode) Clear MSTTC in TCMR to 0 Falling edge detected on CAN bus? TinyCAN is during transmission, reception, or in bus off state? No Interrupt occurred (RHI in TCIRR0 = 1) No Yes Write 0 t
Section 15 Controller Area Network for Tiny (TinyCAN) 15.6 Interrupt Requests The TinyCAN has the following interrupt requests. These interrupts can be masked except for a reset processing interrupt caused by powering on. To mask them, the Mailbox interrupt mask register (MBIMR) and interrupt mask register (IMR) are used. Since these interrupt requests are allocated to the common vector addresses, their sources need to be identified by flags. Table 15.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.7 Test Mode Settings The TinyCAN has various test modes. TCR is used to select each test modes. In the initial configuration, the TinyCAN performs a normal operation. Table 15.5 lists examples of setting the test mode. Table 15.
Section 15 Controller Area Network for Tiny (TinyCAN) Counter Write Error Passive: The TinyCAN can be forced to make a transition to the errorpassive state by writing a value of 127 or higher to the error counter. To write a value to the error counter, set the HLTRQ bit to 1. A value written to TEC is automatically also written to REC; the same value is to be written to TEC and REC. Note that the TinyCAN need to be in halt mode to write a value to TEC and REC.
Section 15 Controller Area Network for Tiny (TinyCAN) 15.9 Usage Notes 1. Since Mailboxes (MCn0, MCn4 to MCn7, and MDn0 to MDn7 (n = 0 to 3)) and LAFM are configured of RAM, initial values are undefined after powering on. Initialize (write 0 or 1) all Mailboxes and LAFM. 2. Set BCR1, BCR0, and the PMR97 and PMR96 bits in TMCR after initializing Mailboxes and LAFM. Otherwise, the TinyCAN starts reception and the receive message ID may be compared with an undefined value of RAM. 3.
Section 15 Controller Area Network for Tiny (TinyCAN) Rev. 4.00 Mar.
Section 16 Synchronous Serial Communication Unit (SSU) Section 16 Synchronous Serial Communication Unit (SSU) The synchronous serial communication unit (SSU) can handle clocked synchronous serial data communication. Figure 16.1 shows a block diagram of the SSU. 16.
Section 16 Synchronous Serial Communication Unit (SSU) 16.3 Register Descriptions The SSU has the following registers.
Section 16 Synchronous Serial Communication Unit (SSU) 16.3.1 SS Control Register H (SSCRH) SSCRH is a register that selects a master or a slave device, enables bidirectional mode, selects open-drain output of the serial data output pin, selects an output value of the serial data output pin, selects the SSCK pin, and selects the SCS pin. Bit Bit Name Initial Value R/W Description 7 MSS 0 R/W Master/Slave Device Select Selects whether this module is used as a master device or a slave device.
Section 16 Synchronous Serial Communication Unit (SSU) Bit Bit Name Initial Value R/W Description 4 SOL 0 R/W Serial Data Output Level Setting Although the value in the last bit of transmit data is retained in the serial data output after the end of transmission, the output level of serial data can be changed by manipulating this bit before or after transmission. When the output level is changed, the SOLP bit should be cleared to 0 and the MOV instruction should be used.
Section 16 Synchronous Serial Communication Unit (SSU) 16.3.2 SS Control Register L (SSCRL) SSCRL is a register that controls module standby, mode, and software reset and selects open-drain output of the SSCK and SCS pins. Bit Bit Name Initial Value R/W Description 7 MSTSSU 0 R/W SSU Module Standby When this bit is 1, the SSU enters the module standby state. In the module standby state, the SSU internal registers other than SSCRL cannot be written to.
Section 16 Synchronous Serial Communication Unit (SSU) Bit Bit Name Initial Value R/W Description 3 CSOS 0 R/W SCS Pin Open-Drain Output Select Selects whether the SCS pin functions as CMOS output or NMOS open-drain output. 0: CMOS output 1: NMOS open-drain output 2 to 0 All 0 Reserved These bits are always read as 0. 16.3.3 SS Mode Register (SSMR) SSMR is a register that selects MSB-first or LSB-first, clock polarity, clock phase, and transfer clock rate.
Section 16 Synchronous Serial Communication Unit (SSU) Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Transfer clock rate select 1 CKS1 0 R/W 0 CKS0 0 R/W Sets transfer clock rate (prescaler division ratio) when the internal clock is selected. 000: φ/256 001: φ/128 010: φ/64 011: φ/32 100: φ/16 101: φ/8 110: φ/4 111: Reserved 16.3.4 SS Enable Register (SSER) SSER is a register that sets transmit enable, receive enable, and interrupt enable.
Section 16 Synchronous Serial Communication Unit (SSU) Bit Bit Name Initial Value R/W Description 1 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, an RXI and an OEI interrupt requests are enabled. 0 CEIE 0 R/W Conflict Error Interrupt Enable When this bit is set to 1, a CEI interrupt request is enabled. 16.3.5 SS Status Register (SSSR) SSSR is a register that sets interrupt flags.
Section 16 Synchronous Serial Communication Unit (SSU) Bit Bit Name Initial Value R/W Description 3 TEND 0 R/W Transmit End [Setting condition] • When the last bit of data is transmitted, the TDRE bit is 1 [Clearing conditions] 2 TDRE 1 R/W • When 0 is written to this bit after reading 1 • When data is written in SSTDR Transmit Data Empty [Setting conditions] • When the TE bit in SSER is 0 • When data transfer is performed from SSTDR to SSTRSR and data can be written in SSTDR [Clear
Section 16 Synchronous Serial Communication Unit (SSU) 16.3.6 SS Receive Data Register (SSRDR) SSRDR is an 8-bit register that stores received serial data. When the SSU has received one byte of serial data, it transfers the received serial data from SSTRSR and the data is stored. After this, SSTRSR is receive-enabled. As SSTRSR and SSRDR function as a double buffer in this way, continuous receive operations are possible. SSRDR is a read-only register and cannot be written to by the CPU.
Section 16 Synchronous Serial Communication Unit (SSU) 16.4 Operation 16.4.1 Transfer Clock Transfer clock can be selected from seven internal clocks and an external clock. When this module is used, the SSCK pin must be selected as a serial clock by setting the SCKS bit in SSCRH to 1. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is in the output state. If transfer is started, the SSCK pin outputs clocks of the transfer rate set in the CKS2 to CKS0 bits in SSMR.
Section 16 Synchronous Serial Communication Unit (SSU) (1) When CPHS = 0, CPOS =0, and SSUMS = 0: SSCK Bit 0 SSO, SSI Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (2) When CPHS = 0 and SSUMS = 1: SSCK (CPOS = 0) SSCK (CPOS = 1) SSO, SSI Bit 0 SCS (3) When CPHS = 1 and SSUMS = 1: SSCK (CPOS = 0) SSCK (CPOS = 1) SSO, SSI Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 SCS Figure 16.
Section 16 Synchronous Serial Communication Unit (SSU) 16.4.3 Relationship between Data Input/Output Pin and Shift Register Relationship of connection between the data input/output pin and SSTRSR changes according to a combination of the MSS bit in SSCRH and the SSUMS bit in SSCRL. It also changes by the BIDE bit in SSCRH. Figure 16.3 shows the relationship.
Section 16 Synchronous Serial Communication Unit (SSU) 16.4.4 Communication Modes and Pin Functions The SSU switches functions of the input/output pin in each communication mode according to the settings of the MSS bit in SSCRH and the RE and TE bits in SSER. Figure 16.2 shows the relationship between communication modes and the input/output pins. Table 16.
Section 16 Synchronous Serial Communication Unit (SSU) 16.4.5 Operation in Clocked Synchronous Communication Mode Initialization in Clocked Synchronous Communication Mode: Figure 16.4 shows the initialization in clocked synchronous communication mode. Before transmitting and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be initialized.
Section 16 Synchronous Serial Communication Unit (SSU) Serial Data Transmission: Figure 16.5 shows an example of the SSU operation for transmission. In serial transmission, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is set as a slave device, it outputs data in synchronized with the input clock.
Section 16 Synchronous Serial Communication Unit (SSU) Start Initialization [1] Read TDRE bit in SSSR No TDRE = 1? [1] After reading SSSR and confirming that the TDRE bit is 1, write transmit data in SSTDR. Then the TDRE bit is automatically cleared to 0. Yes Write transmit data in SSTDR [2] Data transmission continued? Yes [2] Determine whether data transmission is continued.
Section 16 Synchronous Serial Communication Unit (SSU) Serial Data Reception: Figure 16.7 shows an example of the SSU operation for reception. In serial reception, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a slave device, it inputs data in synchronized with the input clock. When the SSU is set as a master device, it outputs a receive clock and starts reception by performing dummy read on SSRDR.
Section 16 Synchronous Serial Communication Unit (SSU) Start Initialization [1] Dummy read on SSRDR [2] Last reception? [1] After setting each register in the SSU, dummy read on SSRDR is performed and reception is started. Yes [2] Determine whether the last one byte of data is received. When the last one byte of data is received, set to stop reception after the data is received.
Section 16 Synchronous Serial Communication Unit (SSU) Serial Data Transmission and Reception: Data transmission and reception is a combined operation of data transmission and reception which are described before. Transmission and reception is started by writing data in SSTDR. When the eighth clock rises or the ORER bit is set to 1 while the TDRE bit is set to 1, transmission and reception is stopped.
Section 16 Synchronous Serial Communication Unit (SSU) Start Initialization [1] Read TDRE in SSSR No TDRE = 1? [1] After reading SSSR and confirming that the TDRE bit is 1, write transmit data in SSTDR. Then the TDRE bit is automatically cleared to 0. Yes Write transmit data in SSTDR [2] No [2] Confirm that the RDRF bit is 1. If the RDRF bit is 1, receive data in SSRDR is read. If the SSRDR bit is read, the RDRF bit is automatically cleared.
Section 16 Synchronous Serial Communication Unit (SSU) 16.4.6 Operation in Four-Line Bus Communication Mode Four-line bus communication mode is a mode which communicates with the four-line bus; a clock line, a data input line, a data output line, and a chip select line. This mode includes bidirectional mode in which the data input line and the data output line function as a single pin. The data input line and the data output line are changed according to the settings of the MSS and BIDE bits in SSCRH.
Section 16 Synchronous Serial Communication Unit (SSU) 16.4.7 Initialization in Four-Line Bus Communication Mode Figure 16.10 shows the initialization in four-line bus communication mode. Before transmitting and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be initialized. Note: When the operating mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the change using the following procedure.
Section 16 Synchronous Serial Communication Unit (SSU) 16.4.8 Serial Data Transmission Figure 16.11 shows an example of the SSU operation for transmission. In serial transmission, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is set as a slave device, the SCS pin is in the low-input state and the SSU outputs data in synchronized with the input clock.
Section 16 Synchronous Serial Communication Unit (SSU) (1) When CPOS = 0 and CPHS = 0: SCS (output) (Hi-Z) SSCK SSO Bit 7 Bit 6 Bit 0 Bit 7 One frame Bit 6 Bit 0 One frame TDRE TEND LSI operation User processing TXI generated Write data in SSTDR TXI generated TEI generated Write data in SSTDR (2) When CPOS = 0 and CPHS = 1: SCS (output) (Hi-Z) SSCK Bit 7 SSO Bit 6 Bit 0 Bit 7 One frame Bit 6 Bit 0 One frame TDRE TEND LSI operation User processing TXI generated Write dat
Section 16 Synchronous Serial Communication Unit (SSU) 16.4.9 Serial Data Reception Figure 16.12 shows an example of the SSU operation for reception. In serial reception, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a slave device, the SCS pin is in the low-input state and inputs data in synchronized with the input clock.
Section 16 Synchronous Serial Communication Unit (SSU) (1) When CPOS = 0 and CPHS = 0: SCS (output) (Hi-Z) SSCK SSI Bit 7 Bit 0 Bit 7 One frame Bit 0 Bit 7 Bit 0 One frame RDRF RSSTP RXI generated LSI operation User processing Dummy read on SSRDR RXI generated Read data in SSRDR Set RSSTP to 1 RXI generated Read data in SSRDR (2) When CPOS = 0 and CPHS = 1: SCS (output) (Hi-Z) SSCK SSI Bit 7 Bit 0 One frame Bit 7 Bit 0 Bit 7 Bit 0 One frame RDRF RSSTP LSI operation User p
Section 16 Synchronous Serial Communication Unit (SSU) 16.4.10 SCS Pin Control and Arbitration When the SSUMS bit in SSCRL is set to 1 and the CSS1 bit in SSCRH is set to 1, the MSS bit in SSCRH is set to 1 and then the arbitration of the SCS pin is checked before starting serial transfer. If the SSU detects that the synchronized internal SCS pin goes low in this period, the CE bit in SSSR is set and the MSS bit is cleared. Note: When a conflict error is set, subsequent transmit operation is not possible.
Section 16 Synchronous Serial Communication Unit (SSU) 16.4.11 Interrupt Requests The SSU has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the common vector address, interrupt sources must be determined by flags. Table 16.3 lists the interrupt requests. Table 16.
Section 16 Synchronous Serial Communication Unit (SSU) 16.5 Usage Note When the output level of serial data is changed according to the values of the SOL and SOLP bit, follow the procedures shown in figure 16.14. Start Clear the SOLP bit in SSCRH to 0. Write the new value noted above to the SOL bit. Set the SOLP bit in SSCRH to 1. Write the new value noted above to the SOL bit. End Figure 16.14 Procedures when Changing Output Level of Serial Data Rev. 4.00 Mar.
Section 17 Subsystem Timer (Subtimer) Section 17 Subsystem Timer (Subtimer) The subtimer is a timer for controlling subsystem which has an on-chip oscillator for supplying system clocks in subactive and subsleep modes and an on-chip 8-bit down counter. Since the subtimer has a prescaler that can set the division ratio by software, it can supply a clock with any frequency. This LSI has an on-chip single-channel subtimer. 17.
Section 17 Subsystem Timer (Subtimer) Figure 17.1 shows a block diagram of the subtimer. For details on the signal to the watchdog timer, refer to section 13, Watchdog Timer.
Section 17 Subsystem Timer (Subtimer) 17.2 Register Descriptions The subtimer has the following registers. • Subtimer control register (SBTCTL) • Subtimer counter (SBTDCNT) • Ring oscillator prescaler setting register (ROPCR) 17.2.1 Subtimer Control Register (SBTCTL) SBTCTL controls oscillation of the on-chip oscillator, subclock output, and counter operation and indicates the operating state. SBTCTL is initialized to H'60.
Section 17 Subsystem Timer (Subtimer) Bit Bit Name Initial Value R/W Description 2 SYSCKS 0 R/W Subclock Supply Enable Enables or disables clock supply to the entire chip when the on-chip oscillator for the subtimer is used. 0: Clock supply is disabled. 1: Clock supply is enabled. 1 SBTIB 0 R/W Subtimer Interrupt Request Enable When this bit is set to 1, an interrupt request caused by the SBTUF flag is enabled.
Section 17 Subsystem Timer (Subtimer) 17.3 Operation 17.3.1 SBTPS Division Ratio Setting The oscillation frequency of the on-chip oscillator ranges from 64 kHz to 850 kHz. To make a subclock with expected frequency by dividing the oscillation frequency, ROPCR must be configured by using following (1) to (6) formulas. The SBTPS division ratio is set as follows. 1.
Section 17 Subsystem Timer (Subtimer) 2TRO = t × n Formula (1) The division ratio of the on-chip oscillator to make the subclock be the setting cycle can be obtained by the following formula. k= TSUB = TRO 2 t×n × TSUB = 2 × TSUB t×n Formula (2) In the subtimer, relationship between the setting values in ROPCR and the division ratio is as follows.
Section 17 Subsystem Timer (Subtimer) • Subclock error In addition to the above rounding error, the subtimer may have a count error caused by time lag between the system clock and the on-chip oscillator. The example is shown below. Table 17.1 Example of Subclock Error Condition: System clock = 10 MHz, on-chip oscillator = 400 kHz, and subclock = 12 kHz Min. Expected Value Max. Count Value n 49 50 51 Division ratio k 34 33 33 Rounding error of division ratio σ +1.
Section 17 Subsystem Timer (Subtimer) The duty cycle of the divided system clock differs according to the ROPCR setting value m. When m is an even number, the duty cycle is 50 %. When m is an odd number, the duty cycle is determined according to the following formula: m+3 × 100 (%) 2m + 4 When m is an odd number, the larger is the setting value m, the closer is the duty cycle to 50 %. Rev. 4.00 Mar.
Section 17 Subsystem Timer (Subtimer) 17.4 Count Operation The subtimer has an 8-bit readable/writable down counter, SBTDCNT. When any value ranging from H′00 to H′FF is written to SBTDCNT and the START bit in SBTCTL is set to 1, the subtimer starts counting down from the configured value in SBTDCNT. When an underflow occurs at H'00, the subtimer requests an interrupt to the CPU. At the end of the exception handling, the subtimer starts counting down again from the configured value written in SBTDCNT.
Section 17 Subsystem Timer (Subtimer) SBTDCNT count value H'FF H'19 H'00 A B C D E F Interrupt request signal A B C D E F G : Write H'19 in SBTDCNT : Set START to 1 to start counting : Underflow occurs and request an interrupt : Underflow occurs again and request an interrupt : Clear START to 0 to stop counting : Set START to 1 to restart counting : Reset generated Figure 17.4 Example of Subtimer Operation Rev. 4.00 Mar.
Section 17 Subsystem Timer (Subtimer) Start count operation setting Write configured value in SBTDCNT Set START bit in SBTCTL to 1 No SBTUF in SBTCTL = 1? Yes Clear SBTUF to 0 Yes Count continued? No Clear START bit in SBTCTL to 0 Clear OSCEB bit in SBTCTL to 0 End count operation Figure 17.5 Count Operation Flowchart Rev. 4.00 Mar.
Section 17 Subsystem Timer (Subtimer) 17.5 Usage Notes 17.5.1 Clock Supply to Watchdog Timer When the on-chip oscillator for the subtimer is used to supply clocks to the watchdog timer, the setting is necessary not only for the subtimer but also for the watchdog timer. For details, refer to section 13, Watchdog Timer. 17.5.2 Writing to ROPCR ROPCR must be written to in active mode with the PCEF bit in SBTCTL set to 1. Otherwise, the subtimer may operate incorrectly. Rev. 4.00 Mar.
Section 18 A/D Converter Section 18 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 18.1. 18.1 • • • • • • • • Features 10-bit resolution Eight input channels Conversion time: at least 3.
Section 18 A/D Converter Module data bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Analog multiplexer 10-bit D/A Bus interface Successive approximations register AVCC Internal data bus A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + φ/4 Control circuit Comparator Sample-andhold circuit ADTRG [Legend] ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D Figure 18.
Section 18 A/D Converter 18.2 Input/Output Pins Table 18.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the analog block in the A/D converter. Table 18.
Section 18 A/D Converter 18.3 Register Descriptions The A/D converter has the following registers. • • • • • • A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 18.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion.
Section 18 A/D Converter 18.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Section 18 A/D Converter Bit Bit Name Initial Value R/W Description 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W Select analog input channels. 0 CH0 0 R/W When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4 100: AN4 101: AN5 101: AN4 and AN5 110: AN6 110: AN4 to AN6 111: AN7 111: AN4 to AN7 18.3.
Section 18 A/D Converter 18.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 18.4.
Section 18 A/D Converter 18.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 18.2 shows the A/D conversion timing. Table 18.3 shows the A/D conversion time. As indicated in figure 18.2, the A/D conversion time includes tD and the input sampling time.
Section 18 A/D Converter Table 18.3 A/D Conversion Time (Single Mode) CKS = 0 Item Symbol Min. A/D conversion start delay time tD Input sampling time tSPL A/D conversion time tCONV CKS = 1 Typ. Max. Min. Typ. Max. 6 — 9 — 31 — 4 — 5 — 15 — 131 — 134 69 — 70 Note: All values represent the number of states. 18.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
Section 18 A/D Converter 18.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 18.4). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 18.5).
Section 18 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 FS 8 Analog input voltage Figure 18.4 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 18.5 A/D Conversion Accuracy Definitions (2) Rev. 4.00 Mar.
Section 18 A/D Converter 18.6 Usage Notes 18.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional) Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional) This LSI can include a power-on reset circuit and low-voltage detection circuit as optional circuits. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits.
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional) 19.1 Features • Power-on reset circuit Uses an external capacitor to generate an internal reset signal when power is first supplied. • Low-voltage detection circuit LVDR: Monitors the power-supply voltage, and generates an internal reset signal when the voltage falls below a specified value. LVDI: Monitors the power-supply voltage, and generates an interrupt when the voltage falls below or rises above respective specified values.
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional) 19.2 Register Descriptions The low-voltage detection circuit has the following registers. • Low-voltage-detection control register (LVDCR) • Low-voltage-detection status register (LVDSR) 19.2.
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional) Bit Bit Name Initial Value R/W Description 0 LVDUE 0 R/W Voltage-Rise-Interrupt Enable 0: Interrupt on the power-supply voltage rising above the selected detection level disabled 1: Interrupt on the power-supply voltage rising above the selected detection level enabled Note: Not initialized by LVDR but initialized by a power-on reset or WDT reset. * Table 19.
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional) 19.2.2 Low-Voltage-Detection Status Register (LVDSR) LVDSR indicates whether the power-supply voltage falls below or rises above the respective specified values. Bit Bit Name Initial Value R/W Description 7 to 2 All 1 Reserved 1 LVDDF 0* R/W LVD Power-Supply Voltage Fall Flag These bits are always read as 1 and cannot be modified. [Setting condition] When the power-supply voltage falls below Vint (D) (typ. = 3.
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional) 19.3 Operation 19.3.1 Power-On Reset Circuit Figure 19.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ. 150 kΩ). Since the state of the RES pin is transmitted within the chip, the prescaler S and the entire chip are in their reset states.
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional) tPWON Vcc Vpor Vss RES Vss PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 19.2 Operational Timing of Power-On Reset Circuit 19.3.2 Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detect) Circuit: Figure 19.3 shows the timing of the LVDR function. The LVDR enters the module-standby state after a power-on reset is canceled.
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional) VCC Vreset VLVDRmin VSS LVDRES PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 19.3 Operational Timing of LVDR Circuit LVDI (Interrupt by Low Voltage Detect) Circuit: Figure 19.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled.
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional) this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously generated. If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function is performed. Vint (U) Vint (D) Vcc Vreset1 VSS LVDINT LVDDE LVDDF LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated Figure 19.4 Operational Timing of LVDI Circuit Rev. 4.00 Mar.
Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional) Procedures for Clearing Settings when Using LVDR and LVDI: To operate or release the low-voltage detection circuit normally, follow the procedure described below. Figure 19.5 shows the timing for the operation and release of the low-voltage detection circuit. 1. To operate the low-voltage detection circuit, set the LVDE bit in LVDCR to 1. 2.
Section 20 Power Supply Circuit Section 20 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V.
Section 20 Power Supply Circuit 20.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and VCC pin, as shown in figure 20.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
Section 21 List of Registers Section 21 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) • Registers are listed from the lower allocation addresses. • The symbol in the register-name column represents a reserved address or range of reserved addresses. Do not attempt to access reserved addresses.
Section 21 List of Registers 21.1 Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register. Note: Access to undefined or reserved addresses should not take place. Correct operation of the access itself or later operations is not guaranteed when such a register is accessed.
Section 21 List of Registers Bit No Address Module Name Data Bus Width Access State MC0[4] 8 H'F624 TinyCAN 8 4 Message control 0 [5] MC0[5] 8 H'F625 TinyCAN 8 4 Message control 0 [6] MC0[6] 8 H'F626 TinyCAN 8 4 Message control 0 [7] MC0[7] 8 H'F627 TinyCAN 8 4 Message control 1 [0] MC1[0] 8 H'F628 TinyCAN 8 4 Message control 1 [4] MC1[4] 8 H'F62C TinyCAN 8 4 Message control 1 [5] MC1[5] 8 H'F62D TinyCAN 8 4 Message control 1 [6] MC1[6] 8 H'F62E TinyC
Section 21 List of Registers Register Name Abbreviation Module Bit No Address Name Data Bus Access Width State Message data 1 [4] MD1[4] 8 H'F64C TinyCAN 8 4 Message data 1 [5] MD1[5] 8 H'F64D TinyCAN 8 4 Message data 1 [6] MD1[6] 8 H'F64E TinyCAN 8 4 Message data 1 [7] MD1[7] 8 H'F64F TinyCAN 8 4 Message data 2 [0] MD2[0] 8 H'F650 TinyCAN 8 4 Message data 2 [1] MD2[1] 8 H'F651 TinyCAN 8 4 Message data 2 [2] MD2[2] 8 H'F652 TinyCAN 8 4 Message data 2 [3]
Section 21 List of Registers Register Name Abbreviation Module Bit No Address Name Data Bus Access Width State Local acceptance filter mask H21 LAFMH21 8 H'F66A TinyCAN 8 4 Local acceptance filter mask H20 LAFMH20 8 H'F66B TinyCAN 8 4 Local acceptance filter mask L31 LAFML31 8 H'F66C TinyCAN 8 4 Local acceptance filter mask L30 LAFML30 8 H'F66D TinyCAN 8 4 Local acceptance filter mask H31 LAFMH31 8 H'F66E TinyCAN 8 4 Local acceptance filter mask H30 LAFMH30 8 H'F66
Section 21 List of Registers Register Name Abbreviation Module Bit No Address Name Data Bus Access Width State General register C_0 GRC_0 16 H'F70C Timer Z 16 2 General register D_0 GRD_0 16 H'F70E Timer Z 16 2 Timer control register_1 TCR_1 8 H'F710 Timer Z 8 2 Timer I/O control register A_1 TIORA_1 8 H'F711 Timer Z 8 2 Timer I/O control register C_1 TIORC_1 8 H'F712 Timer Z 8 2 Timer status register_1 TSR_1 8 H'F713 Timer Z 8 2 Timer interrupt enable register_1
Section 21 List of Registers Register Name Abbreviation Bit No Address Module Name Serial status register_2 SSR_2 8 SCI3_2* SCI3_2* H'F744 Data Bus Width Access State 3 8 3 3 8 3 Receive data register_2 RDR_2 8 H'F745 — — — H'F746 to — H'F75F — — Timer mode register B1 TMB1 8 H'F760 Timer B1 8 2 Timer counter B1 TCB1 8 H'F761 Timer B1 8 2 Timer load register B1 TLB1 8 H'F761 Timer B1 8 2 — — — H'F762 to — H'FF8F — — Flash memory control register 1 FLMC
Section 21 List of Registers Address Module Name Data Bus Width Access State 8 H'FFAD SCI3 8 3 — — H'FFAE, H'FFAF — — — A/D data register A ADDRA 16 H'FFB0 A/D converter 8 3 A/D data register B ADDRB 16 H'FFB2 A/D converter 8 3 A/D data register C ADDRC 16 H'FFB4 A/D converter 8 3 A/D data register D ADDRD 16 H'FFB6 A/D converter 8 3 A/D control/status register ADCSR 8 H'FFB8 A/D converter 8 3 A/D control register ADCR 8 H'FFB9 A/D converter 8 3 — —
Section 21 List of Registers Module Name Data Bus Width Access State H'FFCE, H'FFCF — — — 8 H'FFD0 I/O port 8 2 PUCR5 8 H'FFD1 I/O port 8 2 — — — H'FFD2, H'FFD3 — — — Port data register 1 PDR1 8 H'FFD4 I/O port 8 2 Port data register 2 PDR2 8 H'FFD5 I/O port 8 2 — — — H'FFD6, H'FFD7 — — — Port data register 5 PDR5 8 H'FFD8 I/O port 8 2 Port data register 6 PDR6 8 H'FFD9 I/O port 8 2 Port data register 7 PDR7 8 H'FFDA I/O port 8 2 Port data
Section 21 List of Registers Data Bus Width Access State H'FFED to — H'FFEF — — 8 H'FFF0 Powerdown 8 2 SYSCR2 8 H'FFF1 Powerdown 8 2 IEGR1 8 H'FFF2 Interrupt 8 2 Interrupt edge select register 2 IEGR2 8 H'FFF3 Interrupt 8 2 Interrupt enable register 1 IENR1 8 H'FFF4 Interrupt 8 2 Interrupt enable register 2 IENR2 8 H'FFF5 Interrupt 8 2 Interrupt flag register 1 IRR1 8 H'FFF6 Interrupt 8 2 Interrupt flag register 2 IRR2 8 H'FFF7 Interrupt 8 2 Wakeup i
Section 21 List of Registers 21.2 Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row.
Section 21 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name MC 1 [4] ID20 ID19 ID18 RTR IDE — ID17 ID16 TinyCAN MC 1 [5] ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 MC 1 [6] ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 MC 1 [7] ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 MC 2 [0] DART NMC — — DLC3 DLC2 DLC1 DLC0 MC 2 [4] ID20 ID19 ID18 RTR IDE — ID17 ID16 MC 2 [5] ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 MC
Section 21 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name MD 2 [0] MD07 MD06 MD05 MD04 MD03 MD02 MD01 MD00 TinyCAN MD 2 [1] MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MD 2 [2] MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD 2 [3] MD37 MD36 MD35 MD34 MD33 MD32 MD31 MD30 MD 2 [4] MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD 2 [5] MD57 MD56 MD55 MD54 MD53 MD52 MD51 MD50 MD 2 [6] MD67 MD66 MD65 MD64
Section 21 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name SSCRH MSS BIDE SOOS SOL SOLP SCKS CSS1 CSS0 SSU SSCRL MSTSSU SSUMS SRES SCKOS CSOS — — — SSMR MLS CPOS CPHS — — CKS2 CKS1 CKS0 SSER TE RE RSSTP — TEIE TIE RIE CEIE SSSR — ORER — — TEND TDRE RDRF CE SSRDR SSRDR7 SSRDR6 SSRDR5 SSRDR4 SSRDR3 SSRDR2 SSRDR1 SSRDR0 SSTDR SSTDR7 SSTDR6 SSTDR5 SSTDR4 SSTDR3 SSTDR2 SSTDR1 SSTDR0 SBTCT
Section 21 List of Registers Register Abbreviation Bit 7 TCNT_1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCNT1H7 TCNT1H6 TCNT1H5 TCNT1H4 TCNT1H3 TCNT1H2 TCNT1H1 TCNT1H0 Timer Z TCNT1L7 TCNT1L6 TCNT1L5 TCNT1L4 TCNT1L3 TCNT1L2 TCNT1L1 TCNT1L0 GRA1H7 GRA1H6 GRA1H5 GRA1H4 GRA1H3 GRA1H2 GRA1H1 GRA1H0 GRA1L7 GRA1L6 GRA1L5 GRA1L4 GRA1L3 GRA1L2 GRA1L1 GRA1L0 GRB1H7 GRB1H6 GRB1H5 GRB1H4 GRB1H3 GRB1H2 GRB1H1 GRB1H0 GRB1L7 GRB1L6 GRB1L5 GRB1L4 GRB1L3 GRB1L2 GRB1L1 GRB1L
Section 21 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TCRV0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Timer V TCSRV CMFB CMFA OVF — OS3 OS2 OS1 OS0 TCORA TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0 TCORB TCORB7 TCORB6 TCORB5 TCORB4 TCORB3 TCORB2 TCORB1 TCORB0 TCNTV TCNTV7 TCNTV6 TCNTV5 TCNTV4 TCNTV3 TCNTV2 TCNTV1 TCNTV0 TCRV1 — — — TVEG1 TVEG0 TRGE — ICKS0 SMR COM CHR PE
Section 21 List of Registers Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name PUCR1 PUCR17 PUCR16 PUCR15 PUCR14 — PUCR12 PUCR11 PUCR10 I/O port PUCR5 — — PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PDR1 P17 P16 P15 P14 — P12 P11 P10 PDR2 — — — P24 P23 P22 P21 P20 PDR5 P57 P56 P55 P54 P53 P52 P51 P50 PDR6 P67 P66 P65 P64 P63 P62 P61 P60 PDR7 — P76 P75 P74 — P72 P71 P70 PDR8 P87 P86 P85 — — — — —
Section 21 List of Registers Notes: 1. 2. 3. 4. LVDC: Low-voltage detection circuits (optional) The H8/36037 Group does not have the SCI3_2. WDT: Watchdog timer These bits are reserved in the H8/36037 Group. Rev. 4.00 Mar.
Section 21 List of Registers 21.
Section 21 List of Registers Register Abbreviation Reset Active Sleep Subactive Subsleep Standby Module MC1[4] — — — — — — TinyCAN MC1[5] — — — — — — MC2[1] — — — — — — MC2[2] — — — — — — MC2[3] — — — — — — MC2[4] — — — — — — MC2[5] — — — — — — MC3[1] — — — — — — MC3[2] — — — — — — MC3[3] — — — — — — MC3[4] — — — — — — MC3[5] — — — — — — MD0[1] — — — — — — MD0[2] — — — — — — MD0[3] — — — — — —
Section 21 List of Registers Register Abbreviation Reset Active Sleep Subactive Subsleep Standby Module MD2[4] — — — — — — TinyCAN MD2[5] — — — — — — MD2[6] — — — — — — MD2[7] — — — — — — MD2[8] — — — — — — MD3[1] — — — — — — MD3[2] — — — — — — MD3[3] — — — — — — MD3[4] — — — — — — MD3[5] — — — — — — MD3[6] — — — — — — MD3[7] — — — — — — MD3[8] — — — — — — LAFML0[1] — — — — — — LAFML0[0] — — — —
Section 21 List of Registers Register Abbreviation Reset Active Sleep Subactive Subsleep Standby Module SSMR Initialized — — — — — SSU SSER Initialized — — — — — SSSR Initialized — — — — — SSRDR Initialized — — — — — SSTDR Initialized — — — — — SBTCTL Initialized — — — — — SBTDCNT Initialized — — — — — ROPCR Initialized — — — — — TCR_0 Initialized — — — — — TIORA_0 Initialized — — — — — TIORC_0 Initialized — — — — — TSR_0
Section 21 List of Registers Register Abbreviation Reset Active Sleep Subactive Subsleep Standby Module TMDR Initialized — — — — — Timer Z TPMR Initialized — — — — — TFCR Initialized — — — — — TOER Initialized — — — — — TOCR Initialized — — — — — LVDCR Initialized — — — — — LVDSR Initialized — — — — — SMR_2 Initialized — — Initialized Initialized Initialized BRR_2 Initialized — — Initialized Initialized Initialized SCR3_2 Initialized
Section 21 List of Registers Register Abbreviation Reset Active Sleep Subactive Subsleep Standby Module SSR Initialized — — Initialized Initialized Initialized SCI3 RDR Initialized — — Initialized Initialized Initialized ADDRA Initialized — — Initialized Initialized Initialized ADDRB Initialized — — Initialized Initialized Initialized ADDRC Initialized — — Initialized Initialized Initialized ADDRD Initialized — — Initialized Initialized Initialized ADCSR
Section 21 List of Registers Register Abbreviation Reset Active Sleep Subactive Subsleep Standby Module PCR2 Initialized — — — — — I/O port PCR5 Initialized — — — — — PCR6 Initialized — — — — — PCR7 Initialized — — — — — PCR8 Initialized — — — — — PCR9 Initialized — — — — — SYSCR1 Initialized — — — — — SYSCR2 Initialized — — — — — IEGR1 Initialized — — — — — IEGR2 Initialized — — — — — IENR1 Initialized — — — — — IENR2 I
Section 21 List of Registers Rev. 4.00 Mar.
Section 22 Electrical Characteristics Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +7.0 V * Analog power supply voltage AVCC –0.3 to +7.0 V Input voltage VIN Other than port B Port B Operating temperature Topr –0.3 to VCC +0.3 V –0.3 to AVCC +0.
Section 22 Electrical Characteristics 22.2 Electrical Characteristics (F-ZTAT™ Version) 22.2.1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range: φOSC (MHz) φOSC (MHz) 20.0 850.0 10.0 2.0 64.0 3.0 4.0 5.5 VCC (V) 4.0 5.5 VCC (V) AVCC = 3.3 to 5.5 V • Active mode • Sleep mode • Subactive mode • Subsleep mode AVCC = 3.3 to 5.
Section 22 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range: φ (MHz) 20.0 10.0 2.0 3.3 4.0 AVCC (V) 5.5 VCC = 3.0 to 5.5 V • Active mode • Sleep mode Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used: φosc (MHz) 20.0 16.0 2.0 Vcc(V) 3.0 4.5 5.5 Operation guarantee range Operation guarantee range except A/D conversion accuracy Rev. 4.00 Mar.
Section 22 Electrical Characteristics Range of Power Supply Voltage and Oscillation Frequency when Subtimer is Used: φ (MHz) φSUB (kHz) 20.0 106.25* 1.0 4.0 4.0 5.5 AVcc = 4.0 to 5.5 V • Active mode • Sleep mode Vcc(V) 4.0 AVcc = 4.0 to 5.5 V • Subactive mode • Subsleep mode Note: * Reference value Rev. 4.00 Mar. 15, 2006 Page 444 of 556 REJ09B0026-0400 5.
Section 22 Electrical Characteristics 22.2.2 DC Characteristics Table 22.2 DC Characteristics (1) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Values Item Symbol Input high VIH voltage Applicable Pins Test Condition RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, SCK3, 1 SCK3_2* , SCS, SSCK, TRGV, TMIB1 Min. Typ. Max. Unit VCC = 4.0 to 5.
Section 22 Electrical Characteristics Values Item Input low voltage Symbol VIL Applicable Pins OSC1 VOH Typ. Max. Unit — VCC × 0.3 V — VCC × 0.2 VCC = 4.0 to 5.5 V –0.3 — VCC × 0.3 –0.3 — VCC × 0.2 VCC = 4.0 to 5.5 V –0.3 — 0.5 –0.3 — 0.3 — — P10 to P12, P14 to P17, P20 to P24, P50 to P55, P60 to P67, P70 to P72, P74 to P76, P85 to P87, P90 to P97 VCC = 4.0 to 5.5 V VCC – 1.0 VCC – 0.5 — — P56, P57 VCC = 4.0 to 5.5 V VCC – 2.5 –IOH = 0.1 mA — — VCC = 3.0 to 4.0 V VCC – 2.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Output low voltage VOL P10 to P12, P14 to P17, P20 to P24, P50 to P57, P70 to P72, P74 to P76, P85 to P87 P90 to P97 P60 to P67 Input/ output leakage current | IIL | Min. Typ. Max. Unit VCC = 4.0 to 5.5 V — IOL = 1.6 mA — 0.6 V IOL = 0.4 mA — — 0.4 VCC = 4.0 to 5.5 V — IOL = 20.0 mA — 1.5 VCC = 4.0 to 5.5 V — IOL = 10.0 mA — 1.0 VCC = 4.0 to 5.5 V — IOL = 1.6 mA — 0.4 IOL = 0.4 mA — — 0.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Pull-up MOS current –Ip VCC = 5.0 V, P10 to P12, P14 to P17,P50 to VIN = 0.0 V P55 VCC = 3.0 V, VIN = 0.0 V Input capacitance Cin All input pins except power supply pins Active mode supply current IOPE1 VCC IOPE2 Sleep mode supply current ISLEEP1 ISLEEP2 Subactive mode supply current ISUB Subsleep mode supply current ISUBSP VCC VCC VCC VCC VCC Test Condition Min. Typ. Max. Unit 50.0 — 300.0 µA — 60.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Notes Standby mode supply current ISTBY VCC Subtimer, WDT, 2 and LVD* not used — — 5.0 µA * RAM data retaining voltage VRAM VCC 2.0 — — V Note: 3 Connect the TEST pin to Vss. 1. The H8/36037 Group does not have these pins. 2. The LVD is optional. 3.
Section 22 Electrical Characteristics Table 22.2 DC Characteristics (2) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Item Symbol Allowable output low current (per pin) IOL Allowable output low current (total) ∑IOL Applicable Pins Typ. Max. Unit VCC = 4.0 to 5.5 V — — 2.0 mA Port 6 — — 20.0 Output pins except port 6 — — 0.5 Port 6 — — 10.0 VCC = 4.0 to 5.5 V — — 40.
Section 22 Electrical Characteristics 22.2.3 AC Characteristics Table 22.3 AC Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Values Item Symbol Applicable Pins System clock oscillation frequency fOSC OSC1, OSC2 VCC = 4.0 to 5.5 V System clock (•) cycle time tcyc Test Condition Min. Typ. Max. Unit Reference Figure 2.0 — 20.0 MHz * 2.0 — 10.
Section 22 Electrical Characteristics Item Symbol Applicable Pins RES pin low width tREL RES Values Typ. Max. Unit Reference Figure At power-on and in trc modes other than those below — — ms Figure 22.2 In active mode and 1500 sleep mode operation — — ns Test Condition Min.
Section 22 Electrical Characteristics Table 22.4 Serial Communication Interface (SCI) Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Item Symbol Asynchronous Input clock cycle tscyc Applicable Pins Values Test Condition SCK3, SCK3_2* Clocked synchronous Input clock pulse width tSCKW SCK3, SCK3_2* Transmit data delay time (clocked synchronous) tTXD TXD, TXD_2* VCC = 4.0 to 5.
Section 22 Electrical Characteristics Table 22.5 Controller Area Network for Tiny (TinyCAN) Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Typ. Max. Unit Reference Figure HTXD — — 50 ns Figure 22.6 tHRXS HRXD 50 — — ns tHRXH HRXD 50 — — ns Symbol Transmit data delay time* tHTXD Receive data setup time* Receive data hold time* Note: * Values Min.
Section 22 Electrical Characteristics Table 22.6 Synchronous Communication Unit (SSU) Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), CL = 100 pF, unless otherwise indicated. Item Applicable Symbol Pins Clock cycle tSUCYC Test Condition Min. Values Typ. Max. Unit SSCK 4 — — tCYC Clock high pulse width tHI SSCK 0.4 — 0.6 tSUCYC Clock low pulse width tLO SSCK 0.4 — 0.
Section 22 Electrical Characteristics 22.2.4 A/D Converter Characteristics Table 22.7 A/D Converter Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Item Symbol Applicable Pins Test Condition Values Min. Typ. Max. Unit Reference Figure V * Analog power supply AVCC voltage AVCC 3.3 VCC 5.5 Analog input voltage AVIN AN0 to AN7 VSS – 0.3 — AVCC + 0.
Section 22 Electrical Characteristics Item Symbol Applicable Pins Conversion time (single mode) Test Condition Values Min. AVCC = 4.0 to 134 5.5 V Typ. Max. Unit — — tcyc Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB Reference Figure Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2.
Section 22 Electrical Characteristics 22.2.6 Flash Memory Characteristics Table 22.9 Flash Memory Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Test Condition Values Min. Typ.
Section 22 Electrical Characteristics Item Erasing Symbol Test Condition Values Min. Typ. Max.
Section 22 Electrical Characteristics 22.2.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) Table 22.10 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Values Item Symbol Test Condition Power-supply falling detection voltage Vint (D) LVDSEL = 0 3.3 3.7 — V Power-supply rising detection voltage Vint (U) LVDSEL = 0 — 4.0 4.
Section 22 Electrical Characteristics 22.3 Electrical Characteristics (Masked ROM Version) 22.3.1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range: φOSC (MHz) φOSC (MHz) 20.0 850.0 10.0 2.0 64.0 2.7 4.0 5.5 VCC (V) 4.0 VCC (V) 5.5 AVCC = 3.3 to 5.5 V • Active mode • Sleep mode • Subactive mode • Subsleep mode AVCC = 3.3 to 5.
Section 22 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range: φ (MHz) 20.0 10.0 2.0 3.3 4.0 5.5 AVCC (V) VCC = 2.7 to 5.5 V • Active mode • Sleep mode Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used: φosc (MHz) 20.0 16.0 2.0 Vcc(V) 3.0 4.5 5.5 Operation guarantee range Operation guarantee range except A/D conversion accuracy Rev. 4.00 Mar.
Section 22 Electrical Characteristics Range of Power Supply Voltage and Oscillation Frequency when Subtimer is Used: φ (MHz) φSUB (kHz) 20.0 106.25* 1.0 4.0 4.0 AVcc = 4.0 to 5.5 V • Active mode • Sleep mode 5.5 Vcc(V) 4.0 5.5 Vcc(V) AVcc = 4.0 to 5.5 V • Subactive mode • Subsleep mode Note: * Reference value Rev. 4.00 Mar.
Section 22 Electrical Characteristics 22.3.2 DC Characteristics Table 22.12 DC Characteristics (1) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Values Item Symbol Input high VIH voltage Applicable Pins Test Condition RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG,TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, SCK3, 1 SCK3_2* , SCS, SSCK, TRGV, TMIB1 Min. Typ. Max. Unit VCC = 4.0 to 5.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Input low voltage VIL RES, NMI, WKP0 to WKP5, IRQ0 to IRQ3, ADTRG, TMRIV, TMCIV, FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, SCK3, 1 SCK3_2* , SCS, SSCK, TRGV, TMIB1 Min. Typ. Max. Unit VCC = 4.0 to 5.5 V –0.3 — VCC × 0.2 V –0.3 — VCC × 0.1 VCC = 4.0 to 5.5 V –0.3 RXD, RXD_2* , SSI, SSO, HRXD, P10 to P12, P14 to P17, P20 to P24, P50 to P57, P60 to P67, –0.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Output low voltage VOL P10 to P12, P14 to P17, P20 to P24, P50 to P57, P70 to P72, P74 to P76, P85 to P87, P90 to P97 VCC = 4.0 to 5.5 V — P60 to P67 Min. Typ. Max. Unit — 0.6 V — — 0.4 VCC = 4.0 to 5.5 V — — 1.5 — 1.0 — 0.4 Notes IOL = 1.6 mA IOL = 0.4 mA V IOL = 20.0 mA VCC = 4.0 to 5.5 V — IOL = 10.0 mA VCC = 4.0 to 5.5 V — IOL = 1.6 mA IOL = 0.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Input capacitance Cin All input pins except power supply pins f = 1 MHz, VIN = 0.0 V, Ta = 25°C — — 15.0 pF Active mode supply current IOPE1 VCC Active mode 1 VCC = 5.0 V, fOSC = 20 MHz — 25.0 35.0 mA Active mode 1 VCC = 3.0 V, fOSC = 10 MHz — 10.0 — Active mode 2 VCC = 5.0 V, fOSC = 20 MHz — 1.2 3.0 Active mode 2 VCC = 3.0 V, fOSC = 10 MHz — 0.
Section 22 Electrical Characteristics Values Item Symbol Applicable Pins RAM data retaining voltage VRAM VCC Note: Test Condition Min. Typ. Max. Unit Notes 2.0 — — V Connect the TEST pin to Vss. 1. The H8/36037 Group does not have these pins. 2. The LVD is optional. 3. Pin states during supply current measurement are given below (excluding current in the pull-up MOS transistors and output buffers).
Section 22 Electrical Characteristics Table 22.13 DC Characteristics (2) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Min. Typ. Max. Unit Allowable output low current (per pin) IOL Output pins except port 6 — — 2.0 mA Port 6 — — 20.0 Output pins except port 6 — — 0.5 Port 6 — — 10.0 — — 40.0 Port 6 — — 80.
Section 22 Electrical Characteristics 22.3.3 AC Characteristics Table 22.14 AC Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Values Applicable Test Condition Symbol Pins Min. Typ. Max. Unit Reference Figure System clock oscillation frequency fOSC 2.0 — 20.
Section 22 Electrical Characteristics Item RES pin low width Applicable Test Condition Symbol Pins tREL RES At power-on and in modes other than those below Values Min. Typ. Max. Unit Reference Figure trc — — ms Figure 22.
Section 22 Electrical Characteristics Table 22.15 Serial Communication Interface (SCI) Timing VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Item Input clock cycle Symbol Asynchronous tscyc Applicable Pins Test Condition SCK3, SCK3_2* Clocked synchronous Input clock pulse width tSCKW SCK3, SCK3_2* Transmit data delay time (clocked synchronous) tTXD TXD, TXD_2* VCC = 4.0 to 5.
Section 22 Electrical Characteristics Table 22.16 Controller Area Network for Tiny (TinyCAN) Timing VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Typ. Max. Unit Reference Figure HTXD — — 50 ns Figure 22.6 tHRXS HRXD 50 — — ns tHRXH HRXD 50 — — ns Symbol Transmit data delay time* tHTXD Receive data setup time* Receive data hold time* Note: * Values Min.
Section 22 Electrical Characteristics Table 22.17 Synchronous Communication Unit (SSU) Timing VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), CL = 100 pF, unless otherwise indicated. Item Applicable Symbol Pins Clock cycle tSUCYC Test Condition Min. Values Typ. Max. Unit SSCK 4 — — tCYC Clock high pulse width tHI SSCK 0.4 — 0.6 tSUCYC Clock low pulse width tLO SSCK 0.4 — 0.
Section 22 Electrical Characteristics 22.3.4 A/D Converter Characteristics Table 22.18 A/D Converter Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Item Symbol Applicable Pins Test Condition Values Min. Typ. Max. Unit Reference Figure V * Analog power supply AVCC voltage AVCC 3.3 VCC 5.5 Analog input voltage AVIN AN0 to AN7 VSS – 0.3 — AVCC + 0.
Section 22 Electrical Characteristics Item Symbol Applicable Pins Conversion time (single mode) Values Test Condition AVCC = 4.0 to 5.5 V Nonlinearity error Min. Typ. Max. Unit 134 — — tcyc — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB Reference Figure Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2.
Section 22 Electrical Characteristics 22.3.6 Power-Supply-Voltage Detection Circuit Characteristics (Optional) Table 22.20 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C (regular specifications) or Ta = –40 to +85°C (wide-range specifications), unless otherwise indicated. Values Item Symbol Test Condition Power-supply falling detection voltage Vint (D) LVDSEL = 0 3.3 3.
Section 22 Electrical Characteristics 22.4 Operation Timing t OSC VIH OSC1 VIL t CPH t CPL t CPf t CPr Figure 22.1 System Clock Input Timing VCC VCC × 0.7 OSC1 tREL RES VIL VIL tREL Figure 22.2 RES Low Width Timing NMI IRQ0 to IRQ3 WKP0 to WKP5 ADTRG FTIOA0 to FTIOD0, FTIOA1 to FTIOD1, TMCIV, TMRIV TRGV VIH VIL t IL t IH Figure 22.3 Input Timing Rev. 4.00 Mar.
Section 22 Electrical Characteristics t SCKW SCK3, SCK3_2* t Scyc Note: * The H8/36037 Group does not have this pin. Figure 22.4 SCK3 Input Clock Timing t Scyc 2 VIH or VOH * SCK3, VIL or VOL *2 SCK3_2*1 t TXD TXD, TXD_2*1 (transmit data) VOH* 2 2 VOL * t RXS t RXH RXD, RXD_2*1 (receive data) Notes: 1. The H8/36037 Group does not have these pins. 2. Output timing reference levels Output high: V OH= 2.0 V Output low: V OL= 0.8 V Load conditions are shown in figure 22.12. Figure 22.
Section 22 Electrical Characteristics VOL VOL CK tHTXD HTXD (transmit data) tHTRXS tHTRXH HRXD (receive data) Figure 22.6 TinyCAN Input/Output Timing tHI VIH or VOH SSCK VIH or VOH tLO tSUCYC SSO (output) tOD SSI (input) tSU tH Figure 22.7 SSU Input/Output Timing in Clocked Synchronous Mode Rev. 4.00 Mar.
Section 22 Electrical Characteristics SCS (output) VIH or VOH VIH or VOH tFALL tHI tRISE SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO tSUCYC SSO (output) tOD SSI (input) tSU tH Figure 22.8 SSU Input/Output Timing (Four-Line Bus Communication Mode, Master, CPHS = 1) Rev. 4.00 Mar.
Section 22 Electrical Characteristics SCS (output) VIH or VOH VIH or VOH tFALL tHI tRISE SSCK (output) CPOS = 1 tLO tHI SSCK (output) CPOS = 0 tLO tSUCYC SSO (output) tOD SSI (input) tSU tH Figure 22.9 SSU Input/Output Timing (Four-Line Bus Communication Mode, Master, CPHS = 0) Rev. 4.00 Mar.
Section 22 Electrical Characteristics SCS (input) VIH or VOH VIH or VOH tLEAD tFALL tHI tRISE tLAG SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tLO tSUCYC SSO (input) tSU tH SSI (output) tSA tOD tOR Figure 22.10 SSU Input/Output Timing (Four-Line Bus Communication Mode, Slave, CPHS = 1) Rev. 4.00 Mar.
Section 22 Electrical Characteristics VIH or VOH SCS (input) VIH or VOH tLEAD tFALL tHI tRISE tLAG SSCK (input) CPOS = 1 tLO tHI SSCK (input) CPOS = 0 tSUCYC tLO SSO (input) tSU tH SSI (output) tOD tSA tOD Figure 22.11 SSU Input/Output Timing (Four-Line Bus Communication Mode, Slave, CPHS = 0) Rev. 4.00 Mar.
Section 22 Electrical Characteristics 22.5 Output Load Condition VCC 2.4 kΩ LSI output pin 30 pF 12 k Ω Figure 22.12 Output Load Circuit Rev. 4.00 Mar.
Section 22 Electrical Characteristics Rev. 4.00 Mar.
Appendix Appendix A Instruction Set A.
Appendix Symbol Description ( ), < > Contents of operand Note: General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Symbol Description ↔ Condition Code Notation (cont) Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev. 4.00 Mar.
Appendix Table A.1 Instruction Set 1. Data Transfer Instructions Condition Code MOV.B @(d:16, ERs), Rd B 4 @(d:16, ERs) → Rd8 — — MOV.B @(d:24, ERs), Rd B 8 @(d:24, ERs) → Rd8 — — MOV.B @ERs+, Rd B @ERs → Rd8 ERs32+1 → ERs32 — — MOV.B @aa:8, Rd B 2 @aa:8 → Rd8 — — MOV.B @aa:16, Rd B 4 @aa:16 → Rd8 — — MOV.B @aa:24, Rd B 6 @aa:24 → Rd8 — — MOV.B Rs, @ERd B Rs8 → @ERd — — MOV.B Rs, @(d:16, ERd) B 4 Rs8 → @(d:16, ERd) — — MOV.
Appendix No. of States*1 Condition Code — — @(d:24, ERs) → ERd32 — — @ERs → ERd32 ERs32+4 → ERs32 — — 6 @aa:16 → ERd32 — — 8 @aa:24 → ERd32 — — ERs32 → @ERd — — ERs32 → @(d:16, ERd) — — ERs32 → @(d:24, ERd) — — ERd32–4 → ERd32 ERs32 → @ERd — — 6 ERs32 → @aa:16 — — 8 ERs32 → @aa:24 — — 0 — 0 — POP POP.W Rn W 2 @SP → Rn16 SP+2 → SP — — POP.L ERn L 4 @SP → ERn32 SP+4 → SP — — 0 — PUSH PUSH.W Rn W 2 SP–2 → SP Rn16 → @SP — — 0 — PUSH.
Appendix 2. Arithmetic Instructions No. of States*1 Condition Code Z V C ↔ ↔ — (2) ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ERd32+ERs32 → ERd32 — (2) ↔ ↔ (3) ↔ ↔ Rd16+Rs16 → Rd16 — (1) ERd32+#xx:32 → ERd32 2 Rd8+#xx:8 +C → Rd8 — 2 B 2 Rd8+Rs8 +C → Rd8 — ADDS ADDS.L #1, ERd L 2 ERd32+1 → ERd32 — — — — — — 2 ADDS.L #2, ERd L 2 ERd32+2 → ERd32 — — — — — — 2 ADDS.L #4, ERd L 2 ERd32+4 → ERd32 — — — — — — 2 INC.B Rd B 2 Rd8+1 → Rd8 — — INC.W #1, Rd W 2 Rd16+1 → Rd16 — — INC.
Appendix No. of States*1 Condition Code Advanced V C ERd32–1 → ERd32 — — L 2 ERd32–2 → ERd32 — — ↔ ↔ — 2 DAS.Rd B 2 Rd8 decimal adjust → Rd8 — * ↔ ↔ ↔ 2 DEC.L #2, ERd ↔ ↔ ↔ — * — 2 B 2 Rd8 × Rs8 → Rd16 (unsigned multiplication) — — — — — — 14 W 2 Rd16 × Rs16 → ERd32 (unsigned multiplication) — — — — — — 22 B 4 Rd8 × Rs8 → Rd16 (signed multiplication) — — ↔ W 4 Rd16 × Rs16 → ERd32 (signed multiplication) — — B 2 W DIVXU DIVXU. B Rs, Rd DIVXU.
Appendix No. of States*1 Condition Code W 2 0–Rd16 → Rd16 — NEG.L ERd L 2 0–ERd32 → ERd32 — EXTU EXTU.W Rd W 2 0 → ( of Rd16) — — 0 EXTU.L ERd L 2 0 → ( of ERd32) — — 0 EXTS EXTS.W Rd W 2 ( of Rd16) → ( of Rd16) — — EXTS.L ERd L 2 ( of ERd32) → ( of ERd32) — — Advanced ↔ ↔ ↔ NEG.W Rd Normal C ↔ ↔ ↔ — ↔ ↔ ↔ V ↔ ↔ ↔ ↔ 0–Rd8 → Rd8 2 0 — 2 ↔ 2 0 — 2 ↔ H B 0 — 2 ↔ Z ↔ I NEG NEG.
Appendix 3. Logic Instructions AND.B Rs, Rd B AND.W #xx:16, Rd W 4 AND.W Rs, Rd W AND.L #xx:32, ERd L AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W 4 OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W 4 XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L 4 ERd32⊕ERs32 → ERd32 — — NOT.B Rd B 2 ¬ Rd8 → Rd8 — — NOT.W Rd W 2 ¬ Rd16 → Rd16 — — NOT.
Appendix 4. Shift Instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.L ERd L 2 ROTXR ROTXR.
Appendix 5.
Appendix B BLD #xx:3, @aa:8 B BILD BILD #xx:3, Rd BST BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BST #xx:3, @aa:8 B BIST BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd B BAND #xx:3, @ERd B BAND #xx:3, @aa:8 B BIAND BIAND #xx:3, Rd BOR B B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #
Appendix 6. Branching Instructions Bcc No.
Appendix JMP BSR JSR RTS JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — No.
Appendix 7. System Control Instructions No.
Appendix 8. Block Transfer Instructions EEPMOV No. of States*1 H N Z V C Normal — @@aa @(d, PC) I EEPMOV. B — 4 if R4L ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next — — — — — — 8+ 4n*2 EEPMOV.
REJ09B0026-0400 Rev. 4.00 Mar. 15, 2006 Page 502 of 556 XOR SUBX OR XOR AND MOV B C D E F BILD CMP BIAND BIST BLD BST TRAPA BEQ A BIXOR BAND AND RTE BNE MOV.B Table A.2 (2) LDC 7 ADDX BIOR BXOR OR BOR BSR BCS RTS BCC AND.B ANDC 6 9 BTST DIVXU BLS XOR.B XORC 5 ADD BCLR MULXU BHI OR.B ORC 4 8 7 BNOT DIVXU MULXU 5 BSET BRN BRA 6 LDC 3 Table A.2 Table A.2 Table A.2 Table A.2 (2) (2) (2) (2) STC NOP 4 3 2 1 0 2 1 Table A.
MOV BRA 58 7A DAS 1F MOV SUBS 1B 79 DEC 1A NOT 1 ADD ADD BRN ROTXR 13 17 ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 CMP CMP BHI 2 SUB SUB BLS NOT ROTXR ROTXL SHLR SHLL 3 OR OR BCC LDC/STC 4 1st byte 2nd byte AH AL BH BL XOR XOR BCS DEC EXTU INC 5 AND AND BNE 6 BEQ DEC EXTU INC 7 BVC SUB NEG 9 BVS ROTR ROTL SHAR SHAL ADDS SLEEP 8 BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Tab
REJ09B0026-0400 Rev. 4.00 Mar. 15, 2006 Page 504 of 556 DIVXS 3 BSET 7Faa7 * 2 BNOT BNOT BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle.
Appendix Table A.3 Number of States Required for Execution Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2, 3, or 4* Word data access SM 2, 3, or 4* Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. See section 21.1, Register Addresses (Address Order). Rev. 4.00 Mar.
Appendix Table A.4 Number of Cycles in Each Instruction Instruction Mnemonic Instruction Fetch I ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND.L ERs, ERd 2 ANDC #xx:8, CCR 1 AND ANDC BAND Bcc Stack Branch Addr.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K BTST BTST #xx:3, Rd 1 BTST #xx:3, @ERd 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @ERd 2 1 BTST Rn, @aa:8 2 1 BXOR #xx:3, Rd 1 BXOR #xx:3, @ERd 2 1 BXOR #xx:3, @aa:8 2 1 CMP.B #xx:8, Rd 1 CMP.B Rs, Rd 1 CMP.W #xx:16, Rd 2 CMP.W Rs, Rd 1 CMP.L #xx:32, ERd 3 CMP.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K INC INC.B Rd 1 INC.W #1/2, Rd 1 INC.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K MOV MOV.B Rs, @aa:16 2 1 MOV.B Rs, @aa:24 3 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @ERs, Rd 1 1 MOV.W @(d:16,ERs), Rd 2 1 MOV.W @(d:24,ERs), Rd 4 1 MOV.W @ERs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W @aa:24, Rd 3 1 MOV.W Rs, @ERd 1 1 MOV.W Rs, @(d:16,ERd) 2 1 MOV.W Rs, @(d:24,ERd) 4 1 MOV.W Rs, @-ERd 1 1 MOV.W Rs, @aa:16 2 1 MOV.W Rs, @aa:24 3 1 MOV.L #xx:32, ERd 3 MOV.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K MULXS MULXS.B Rs, Rd 2 12 MULXS.W Rs, ERd 2 20 MULXU.B Rs, Rd 1 12 MULXU.W Rs, ERd 1 20 NEG.B Rd 1 NEG.W Rd 1 NEG.L ERd 1 NOP 1 MULXU NEG NOP NOT OR NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 OR.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K Stack ROTXR ROTXR.B Rd 1 ROTXR.W Rd 1 Byte Data Word Data Internal Access L Access M Operation N ROTXR.L ERd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAR SHLL SHLR SHAL.B Rd 1 SHAL.W Rd 1 SHAL.L ERd 1 SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 SHLR.
Appendix Instruction Branch Instruction Mnemonic Fetch I Addr. Read Operation J K SUBX SUBX #xx:8, Rd 1 SUBX. Rs, Rd 1 TRAPA TRAPA #xx:2 2 XOR XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XOR.L ERs, ERd 2 XORC #xx:8, CCR 1 XORC 1 Stack 2 Byte Data Word Data Internal Access L Access M Operation N 4 Notes: 1. n: Specified value in R4L and R4. The source and destination operands are accessed n+1 times respectively. 2.
Appendix A.4 Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes @@aa:8 — — — — — — — WL — BWL BWL — @(d:16.PC) — — — @aa:24 — — — B @aa:16 — — — @aa:8 @ERn+/@ERn @(d:24.ERn) @ERn BWL BWL BWL BWL BWL BWL — — — — — — — — — — — — @(d:8.PC) Data MOV transfer POP, PUSH instructions MOVFPE, Rn Instructions #xx Functions @(d:16.
Appendix Appendix B I/O Port Block Diagrams B.1 I/O Port Block Diagrams RES goes low in a reset, and SBY goes low at reset and in standby mode. Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.1 Port 1 Block Diagram (P17) Rev. 4.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P14, P16) Rev. 4.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TMIB1 [Legend] PUCR : Port pull-up control register PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.3 Port 1 Block Diagram (P15) Rev. 4.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PDR PCR [Legend] PUCR : Port pull-up control register PDR : Port data register PCR : Port control register Figure B.4 Port 1 Block Diagram (P12, P11, P10) Rev. 4.00 Mar.
Appendix Internal data bus SBY PMR PDR PCR [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.5 Port 2 Block Diagram (P24, P23) Rev. 4.00 Mar.
Appendix Internal data bus SBY PMR PDR PCR SCI3 TxD [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.6 Port 2 Block Diagram (P22) Rev. 4.00 Mar.
Appendix SBY Internal data bus PDR PCR SCI3 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.7 Port 2 Block Diagram (P21) Rev. 4.00 Mar.
Appendix SBY SCI3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.8 Port 2 Block Diagram (P20) Rev. 4.00 Mar.
Appendix Internal data bus SBY PMR PDR PCR [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Figure B.9 Port 5 Block Diagram (P57, P56) Rev. 4.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.10 Port 5 Block Diagram (P55) Rev. 4.00 Mar.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.11 Port 5 Block Diagram (P54 to P55) Rev. 4.00 Mar.
Appendix Internal data bus SBY Timer Z Output control signals A to D PDR PCR FTIOA to FTIOD [Legend] PDR : Port data register PCR : Port control register Figure B.12 Port 6 Block Diagram (P67 to P60) Rev. 4.00 Mar.
Appendix Internal data bus SBY Timer V OS3 OS2 OS1 OS0 PDR PCR TMOV [Legend] PDR: Port data register PCR: Port control register Figure B.13 Port 7 Block Diagram (P76) Rev. 4.00 Mar.
Appendix Internal data bus SBY PDR PCR Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register Figure B.14 Port 7 Block Diagram (P75) Rev. 4.00 Mar.
Appendix Internal data bus SBY PDR PCR Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register Figure B.15 Port 7 Block Diagram (P74) Rev. 4.00 Mar.
Appendix Internal data bus SBY PMR PDR PCR SCI3_2* TxD [Legend] PMR : Port mode register PDR : Port data register PCR : Port control register Note: The H8/36037 Group does not have the SCI3_2. Figure B.16 Port 7 Block Diagram (P72) Rev. 4.00 Mar.
Appendix SBY Internal data bus PDR PCR SCI3_2* RE RxD [Legend] PDR : Port data register PCR : Port control register Note: The H8/36037 Group does not have the SCI3_2. Figure B.17 Port 7 Block Diagram (P71) Rev. 4.00 Mar.
Appendix SBY SCI3_2* SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR : Port data register PCR : Port control register Note: The H8/36037 Group does not have the SCI3_2. Figure B.18 Port 7 Block Diagram (P70) Rev. 4.00 Mar.
Appendix Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.19 Port 8 Block Diagram (P87 to P85) Rev. 4.00 Mar.
Appendix SBY TinyCAN HTXD output control Internal data bus PDR PCR HTXD [Legend] PDR : Port data register PCR : Port control register Figure B.20 Port 9 Block Diagram (P97) Rev. 4.00 Mar.
Appendix RST SBY TinyCAN HRXD input control Internal data bus PDR PCR HRXD HWKPU [Legend] PDR : Port data register PCR : Port control register Figure B.21 Port 9 Block Diagram (P96) Rev. 4.00 Mar.
Appendix Internal data bus SBY PDR PCR [Legend] PMR : Port mode register PCR : Port control register Figure B.22 Port 9 Block Diagram (P94, P95) Rev. 4.00 Mar.
Appendix SBY SSU SSI output control SSI input control SSINMOS opendrain output control Internal data bus PDR PCR SSI output SSI input [Legend] PDR : Port data register PCR : Port control register Figure B.23 Port 9 Block Diagram (P93) Rev. 4.00 Mar.
Appendix SBY SSU SSO output control SSO input control SSONMOS opendrain output control Internal data bus PDR PCR SSO output SSO input [Legend] PDR : Port data register PCR : Port control register Figure B.24 Port 9 Block Diagram (P92) Rev. 4.00 Mar.
Appendix SBY SSU SSCK output control SSCK input control SSCKNMOS opendrain output control Internal data bus PDR PCR SSCK output SSCK input [Legend] PDR : Port data register PCR : Port control register Figure B.25 Port 9 Block Diagram (P91) Rev. 4.00 Mar.
Appendix SBY SSU SCS output control SCS input control SCSNMOS opendrain output control Internal data bus PDR PCR SCS output SCS input [Legend] PDR : Port data register PCR : Port control register Figure B.26 Port 9 Block Diagram (P90) Rev. 4.00 Mar.
Appendix Internal data bus A/D converter CH3 to CH0 DEC VIN Figure B.27 Port B Block Diagram (PB7 to PB0) Rev. 4.00 Mar.
Appendix B.
Appendix Appendix C Product Code Lineup Package Code Product Classification H8/36057 Flash memory version Masked ROM version H8/36054 Flash memory version Masked ROM version H8/36037 Flash memory version Masked ROM version H8/36036 H8/36035 Masked ROM version Masked ROM version QFP-64 (FP-64A) LQFP-64 (FP-64K) Standard product HD64F36057H HD64F36057FZ Product with POR & LVDC HD64F36057GH HD64F36057GFZ Standard product HD64336057(***)H HD64336057(***)FZ Product with POR & LVDC HD643
Appendix Package Code Product Classification H8/36034 Flash memory version Masked ROM version H8/36033 H8/36032 Masked ROM version Masked ROM version QFP-64 (FP-64A) LQFP-64 (FP-64K) Standard product HD64F36034H HD64F36034FZ Product with POR & LVDC HD64F36034GH HD64F36034GFZ Standard product HD64336034(***)H HD64336034(***)FZ Product with POR & LVDC HD64336034G(***)H HD64336034G(***)FZ Standard product HD64336033(***)H HD64336033(***)FZ Product with POR & LVDC HD64336033G(***)H HD
Appendix Appendix D Package Dimensions The package dimensions that are shown in the Renesas Semiconductor Packages Data Book have priority. Unit: mm 12.0 ± 0.2 10 48 33 32 0.5 12.0 ± 0.2 49 64 17 0.08 *Dimension including the plating thickness Base material dimension *0.145 ± 0.05 0.125 ± 0.04 1.25 1.40 0.08 M 1.70 Max 16 0.10 ± 0.10 1 *0.20 ± 0.05 0.18 ± 0.04 1.0 0° − 8° 0.5 ± 0.2 Package Code JEDEC EIAJ Mass (reference value) FP-64K − Conforms 0.3 g Figure D.
Appendix Unit: mm 17.2 ± 0.3 14 33 48 32 0.8 17.2 ± 0.3 49 64 17 1 0.10 *Dimension including the plating thickness Base material dimension *0.17 ± 0.05 0.15 ± 0.04 3.05 Max 1.0 2.70 0.15 M 0.10 +0.15 - 0.10 *0.37 ± 0.08 0.35 ± 0.06 16 REJ09B0026-0400 0° − 8° 0.8 ± 0.3 Package Code JEDEC EIAJ Mass (reference value) Figure D.2 FP-64A Package Dimensions Rev. 4.00 Mar. 15, 2006 Page 548 of 556 1.6 FP-64A − Conforms 1.
Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Preface vii Added When using an on-chip emulator (E7, E8) for H8/36057 and H8/36037 program development and debugging, the following restrictions must be noted. Notes 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, P86, and P87 cannot be used. In order to use these pins, additional hardware must be provided on the user board. 3.
Item Page Revision (See Manual for Details) 12.3.7 Timer Counter (TCNT) 177 Added ….The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. TCNT is initialized to H'0000. Figure 12.17 Example of Input Capture Operation 196 Amended Counter cleared by FTIOB input (falling edge) Time 12.4.4 Synchronous Operation 199 Added Figure 12.20 shows an example of synchronous operation. In this example, …. set for the channel 1 counter clearing source.
Item Page Revision (See Manual for Details) Figure 12.45 Example of Output Disable Timing of Timer Z by External Trigger 230 Amended φ WKP4 TOER N Timer Z output pin 13.2.1 Timer Control/Status Register WD (TCSRWD) 246 H'FF Timer Z output I/O port Amended Bit Bit Name Description 4 TCSRWE Timer Control/Status Register WD Write Enable The WDON and WRST bits can be written when the TCSRWE bit is set to 1. When writing data to this bit, the value for bit 5 must be 0. 16.
Item Page Revision (See Manual for Details) Table 22.2 DC Characteristics (1) 449 Amended Table 22.12 DC Characteristics (1) Note: 3. Pin states during current consumption measurement are given below (excluding current in the pull-up MOS transistors and output buffers). Mode RES Pin Internal State Active mode 1 VCC Operates Active mode 2 Only timers operate VCC Sleep mode 2 Figure 22.8 SSU Input/Output Timing (Four-Line Bus Communication Mode, Master, CPHS = 1) to Figure 22.
Index A A/D converter ......................................... 391 Sample-and-hold circuit...................... 398 Scan mode........................................... 397 Single mode ........................................ 397 Address break ........................................... 67 Addressing modes..................................... 32 Absolute address................................... 33 Immediate ............................................. 34 Memory indirect ................................
LVDR (reset by low voltage detect) circuit...................................................... 409 M Memory map ............................................ 10 Module standby function .......................... 87 O On-board Programming modes................. 95 Operation field.......................................... 31 P Package....................................................... 2 Pin arrangement.......................................... 4 Power-down modes ..................................
PDR1 .......................... 113, 423, 431, 438 PDR2 .......................... 117, 423, 431, 438 PDR5 .......................... 122, 423, 431, 438 PDR6 .......................... 127, 423, 431, 438 PDR7 .......................... 132, 423, 431, 438 PDR8 .......................... 136, 423, 431, 438 PDR9 .......................... 138, 423, 431, 438 PDRB.......................... 141, 423, 431, 438 PMR1.......................... 112, 423, 431, 438 PMR3.......................... 118, 423, 431, 438 PMR5.
Programming units ............................... 89 Programming/erasing in user program mode ..................................................... 98 Software protection............................. 105 S Serial communication interface 3 (SCI3) ..................................................... 251 Asynchronous mode ........................... 270 Bit rate ................................................ 261 Break .................................................. 292 Clocked synchronous mode..........
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/36057 Group, H8/36037 Group Publication Date: Rev.1.00, Jun. 27, 2003 Rev.4.00, Mar. 15, 2006 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
16 H8/36057Group, H8/36037Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0026-0400
