Datasheet

Section 5 Clock Pulse Generators
Rev. 4.00 Mar. 15, 2006 Page 73 of 556
REJ09B0026-0400
Section 5 Clock Pulse Generators
The clock pulse generator is provided on-chip, including both a system clock pulse generator and
a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator,
a duty correction circuit, and a system clock divider. The subclock pulse generator consists of an
on-chip oscillator, division ratio setting register, and a sub-clock divider.
Figure 5.1 shows a block diagram of the clock pulse generators.
System
clock
oscillator
On-chip
oscillator
Ring
oscillator
prescaler
setting register
(ROPCR)
8 bits
Subclock
divider
Duty
correction
circuit
System
clock
divider
Prescaler S
(13 bits)
OSC
1
OSC
2
System clock pulse generator
φ
OSC
(f
OSC
)
φ
OSC
(f
OSC
)
φ
SUB
φ
w
(fw)
φ/2
to
φ/8192
Watchdog
timer
φ
φ
OSC
/8
φ
OSC
φ
OSC
/16
φ
W
/4
φ
W
/2
φ
W
/8
φ
OSC
/32
φ
OSC
/64
Subclock pulse generator
Figure 5.1 Block Diagram of Clock Pulse Generators
The basic clock signals that drive the CPU and on-chip peripheral modules are system clocks (φ)
and subclocks (φ
SUB
). The system clock is divided by the prescaler S to become a clock signal from
φ/8192 to φ/2, which is provided to the on-chip peripheral modules. The output (φ
W
) of the division
ratio setting register (ROPCR) for the on-chip clock pulse generator can be used as one of the
input clocks for the watchdog timer.