Datasheet

Section 6 Power-Down Modes
Rev. 4.00 Mar. 15, 2006 Page 80 of 556
REJ09B0026-0400
Bit Bit Name
Initial
Value R/W Description
1
0
SA1
SA0
0
0
R/W
R/W
Subactive Mode Clock Select 1 and 0
These bits select the operating clock frequency in
subactive and subsleep modes. The operating clock
frequency changes to the set frequency after the SLEEP
instruction is executed.
00: φ
W
/8
01: φ
W
/4
1X: φ
W
/2
[Legend]
X: Don't care.
6.1.3 Module Standby Control Register 1 (MSTCR1)
MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units.
Bit Bit Name
Initial
Value R/W Description
7, 6  All 0  Reserved
These bits are always read as 0.
5 MSTS3 0 R/W SCI3 Module Standby
The SCI3 enters standby mode when this bit is set to 1.
4 MSTAD 0 R/W A/D Converter Module Standby
The A/D converter enters standby mode when this bit is
set to 1.
3 MSTWD 0 R/W Watchdog Timer Module Standby
The watchdog timer enters standby mode when this bit is
set to 1. When the internal oscillator is selected for the
watchdog timer clock, the watchdog timer operates
regardless of the setting of this bit.
2  0  Reserved
This bit is always read as 0.
1 MSTTV 0 R/W Timer V Module Standby
The timer V enters standby mode when this bit is set to 1.
0  0  Reserved
This bit is always read as 0.