Datasheet

Section 6 Power-Down Modes
Rev. 4.00 Mar. 15, 2006 Page 81 of 556
REJ09B0026-0400
6.1.4 Module Standby Control Register 2 (MSTCR2)
MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units.
Bit Bit Name
Initial
Value R/W Description
7 MSTS3_2 0 R/W SCI3_2 Module Standby
The SCI3_2 enters standby mode when this bit is set to
1.
Note: This bit is reserved in the H8/36037 Group. This bit
is always read as 0.
6, 5  All 0  Reserved
These bits are always read as 0.
4 MSTTB1 0 R/W Timer B1 Module Standby
The timer B1 enters standby mode when this bit is set to
1.
3, 2  All 0  Reserved
These bits are always read as 0.
1 MSTTZ 0 R/W Timer Z Module Standby
The timer Z enters standby mode when this bit is set to 1.
0  0  Reserved
This bit is always read as 0.