Datasheet

Section 12 Timer Z
Rev. 4.00 Mar. 15, 2006 Page 184 of 556
REJ09B0026-0400
Bit Bit Name
Initial
Value R/W Description
0 IMFA 0 R/W Input Capture/Compare Match Flag A
[Setting conditions]
• When TCNT = GRA and GRA is functioning as output
compare register
• When TCNT value is transferred to GRA by input
capture signal and GRA is functioning as input
capture register
[Clearing condition]
• When 0 is written to IMFA after reading IMFA = 1
Note: Bit 5 is not the UDF flag in TSR_0. It is a reserved bit. It is always read as 1.
12.3.12 Timer Interrupt Enable Register (TIER)
TIER enables or disables interrupt requests for overflow or GR compare match/input capture.
Timer Z has two TIER registers, one for each channel.
Bit Bit Name
Initial
Value R/W Description
7 to 5  All 1  Reserved
These bits are always read as 1.
4 OVIE 0 R/W Overflow Interrupt Enable
0: Interrupt requests (OVI) by OVF or UDF flag are
disabled
1: Interrupt requests (OVI) by OVF or UDF flag are
enabled
3 IMIED 0 R/W Input Capture/Compare Match Interrupt Enable D
0: Interrupt requests (IMID) by IMFD flag are disabled
1: Interrupt requests (IMID) by IMFD flag are enabled
2 IMIEC 0 R/W Input Capture/Compare Match Interrupt Enable C
0: Interrupt requests (IMIC) by IMFC flag are disabled
1: Interrupt requests (IMIC) by IMFC flag are enabled
1 IMIEB 0 R/W Input Capture/Compare Match Interrupt Enable B
0: Interrupt requests (IMIB) by IMFB flag are disabled
1: Interrupt requests (IMIB) by IMFB flag are enabled