Datasheet

Section 12 Timer Z
Rev. 4.00 Mar. 15, 2006 Page 197 of 556
REJ09B0026-0400
Input Capture Signal Timing: Input capture on the rising edge, falling edge, or both edges can
be selected through settings in TIOR. Figure 12.18 shows the timing when the rising edge is
selected. The pulse width of the input capture signal must be at least two system clock (φ) cycles.
TCNT
Input capture signal
Input capture input
GR
N
N
φ
Figure 12.18 Input Capture Signal Timing