Datasheet

Section 12 Timer Z
Rev. 4.00 Mar. 15, 2006 Page 200 of 556
REJ09B0026-0400
12.4.5 PWM Mode
In PWM mode, PWM waveforms are output from the FTIOB, FTIOC, and FTIOD output pins
with GRA as a cycle register and GRB, GRC, and GRD as duty registers. The initial output level
of the corresponding pin depends on the setting values of TOCR and POCR. Table 12.3 shows an
example of the initial output level of the FTIOB0 pin.
The output level is determined by the POLB to POLD bits corresponding to POCR. When POLB
is 0, the FTIOB output pin is set to 0 by compare match B and set to 1 by compare match A. When
POLB is 1, the FTIOB output pin is set to 1 by compare match B and cleared to 0 by compare
match A. In PWM mode, maximum 6-phase PWM outputs are possible.
Figure 12.21 shows an example of the PWM mode setting procedure.
Table 12.3 Initial Output Level of FTIOB0 Pin
TOB0 POLB Initial Output Level
0 0 1
0 1 0
1 0 0
1 1 1