Datasheet

Section 12 Timer Z
Rev. 4.00 Mar. 15, 2006 Page 234 of 556
REJ09B0026-0400
12.5.2 Status Flag Clearing Timing
The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 12.51 shows the
timing in this case.
Address TSR address
φ
WTSR
(internal write signal)
IMF, OVF
ITMZ
Figure 12.51 Status Flag Clearing Timing