Datasheet

Section 12 Timer Z
Rev. 4.00 Mar. 15, 2006 Page 235 of 556
REJ09B0026-0400
12.6 Usage Notes
Contention between TCNT Write and Clear Operations: If a counter clear signal is generated
in the T
2
state of a TCNT write cycle, TCNT clearing has priority and the TCNT write is not
performed. Figure 12.52 shows the timing in this case.
T1 T2
TCNT
TCNT write cycle
TCNT address
WTCNT
(internal write signal)
Clearing has priority.
Counter clear signal
N H'0000
φ
Figure 12.52 Contention between TCNT Write and Clear Operations