Datasheet

Section 12 Timer Z
Rev. 4.00 Mar. 15, 2006 Page 237 of 556
REJ09B0026-0400
Contention between GR Write and Compare Match: If a compare match occurs in the T
2
state
of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure 12.54
shows the timing in this case.
T 1 T 2
GR N M
TCNT
GR write cycle
GR address
WGR
(internal write signal)
GR write data
Compare match
signal
Disabled
N N+1
φ
Figure 12.54 Contention between GR Write and Compare Match