Datasheet

Section 12 Timer Z
Rev. 4.00 Mar. 15, 2006 Page 239 of 556
REJ09B0026-0400
Contention between GR Read and Input Capture: If an input capture signal is generated in the
T
1
state of a GR read cycle, the data that is read will be transferred before input capture transfer.
Figure 12.56 shows the timing in this case.
T 1 T 2
GR
GR read cycle
GR address
Internal read
signal
Input capture
signal
Internal data
bus
X
X
M
φ
Figure 12.56 Contention between GR Read and Input Capture