Datasheet

Section 13 Watchdog Timer
Rev. 4.00 Mar. 15, 2006 Page 245 of 556
REJ09B0026-0400
Section 13 Watchdog Timer
The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
The block diagram of the watchdog timer is shown in figure 13.1.
φ
φw(fw)
From subtimer
Internal reset
signal
PSS TCWD
TMWD
TCSRWD
Internal data bus
[Legend]
TCSRWD: Timer control/status register WD
TCWD: Timer counter WD
PSS: Prescaler S
TMWD: Timer mode register WD
Internal
oscillator
CLK
Figure 13.1 Block Diagram of Watchdog Timer
13.1 Features
• Selectable from nine counter input clocks.
Eight internal clock sources (φ/64, φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, and φ/8192)
or the internal oscillator (WDT and SBT) can be selected as the timer-counter clock. When the
internal oscillator is selected, it can operate as the watchdog timer in any operating mode.
• Reset signal generated on counter overflow
An overflow period of 1 to 256 times the selected clock can be set.
[Legend]
WDT: Watchdog timer
SBT: Subtimer