Datasheet

Section 15 Controller Area Network for Tiny (TinyCAN)
Rev. 4.00 Mar. 15, 2006 Page 297 of 556
REJ09B0026-0400
15.2 Input/Output Pins
Table 15.1 shows the TinyCAN pin configuration.
TinyCAN pins must be configured in configuration mode (while the RSTRQ bit in MCR and the
RESET bit in GSR are both set to 1). A bus driver is necessary for the interface between the
TinyCAN pins and the CAN bus. A Renesas Technology HA13721 compatible model is
recommended.
Table 15.1 Pin Configuration
Name Abbreviation I/O Function
TinyCAN transmit data pin HTXD Output CAN bus transmission pin
TinyCAN receive data pin HRXD Input CAN bus reception pin
15.3 Register Descriptions
The TinyCAN has the following registers.
• Test control register (TCR)
• Master control register (MCR)
• TinyCAN module control register (TCMR)
• General status register (GSR)
• Bit configuration registers 0, 1 (BCR0, BCR1)
• Mailbox configuration register (MBCR)
• Transmit pending register (TXPR)
• Transmit pending cancel register (TXCR)
• Transmit acknowledge register (TXACK)
• Abort acknowledge register (ABACK)
• Data frame receive complete register (RXPR)
• Remote request register (RFPR)
• Unread message status register (UMSR)
• TinyCAN interrupt registers 0, 1 (TCIRR0, TCIRR1)
• Mailbox interrupt mask register (MBIMR)
• TinyCAN interrupt mask registers 0, 1 (TCIMR0, TCIMR1)
• Transmit error counter (TEC)
• Receive error counter (REC)