Datasheet

Section 15 Controller Area Network for Tiny (TinyCAN)
Rev. 4.00 Mar. 15, 2006 Page 302 of 556
REJ09B0026-0400
15.3.4 General Status Register (GSR)
GSR indicates the status of the CAN bus. Each bit in GSR is set or cleared to notify the CPU of
the TinyCAN status.
Bit Bit Name
Initial
Value R/W Description
7, 6 — All 0 — Reserved
These bits are always read as 0.
5 ERPS 0 R Error Passive Status Flag
Indicates whether the CDLC is in the error-passive state.
This flag is always set to 1 when the CDLC is in the error-
passive state or bus off state.
[Setting condition]
When TEC ≥ 128 or REC ≥ 128
[Clearing condition]
When the error-active state is entered
4 HALT 0 R Halt Status Flag
Indicates whether the TinyCAN is in halt mode.
[Setting condition]
When the CAN bus receives an intermission frame or the
bus is idle with the HLTRQ bit in MCR set to 1
[Clearing condition]
When the HLTRQ bit is cleared to 0 and halt mode is
exited
3 RESET 1 R Reset Status Flag
Indicates whether the TinyCAN is in reset mode.
[Setting condition]
When the TinyCAN is in the reset state
[Clearing condition]
When communication with the CAN bus is enabled after
the reset procedure completes