Datasheet

Section 15 Controller Area Network for Tiny (TinyCAN)
Rev. 4.00 Mar. 15, 2006 Page 315 of 556
REJ09B0026-0400
15.3.15 Mailbox Interrupt Mask Register (MBIMR)
MBIMR controls enabling or disabling of individual Mailbox interrupt requests. Setting and
clearing each status flag has nothing to do with the configuration of bits in MBIMR.
Bit Bit Name
Initial
Value R/W Description
7 to 4 — All 1 — Reserved
These bits are always read as 1.
3
2
1
0
MB3
MB2
MB1
MB0
1
1
1
1
R/W
R/W
R/W
R/W
These flags enable or disable individual Mailbox interrupt
requests.
The interrupt source in a transmit Mailbox is clearing of
the corresponding bit in TXPR caused by transmission
end or transmission cancellation. The interrupt source in
a receive Mailbox is setting of the corresponding bit in
RXPR or RFPR caused by reception end.
0: An interrupt request in the corresponding Mailbox is
enabled
1: An interrupt request in the corresponding Mailbox is
disabled
15.3.16 TinyCAN Interrupt Mask Registers 0, 1 (TCIMR0, TCIMR1)
TCIMR controls enabling or disabling of TCIRR interrupt requests. When the corresponding bit is
set to 1, the interrupt request is masked. This register corresponds to TCIRR.
• TCIMR0
Bit Bit Name
Initial
Value R/W Description
7 OVLIM 1 R/W Overload Frame Transmit Interrupt Mask
Enables or disables an interrupt request for overload
frame transmission.
0: The interrupt request for the overload frame
transmission is enabled
1: The interrupt request for the overload frame
transmission is disabled