Datasheet

Section 15 Controller Area Network for Tiny (TinyCAN)
Rev. 4.00 Mar. 15, 2006 Page 324 of 556
REJ09B0026-0400
15.5 Operation
15.5.1 TinyCAN Initial Settings
Figure 15.4 shows a flowchart for reset clearing of the TinyCAN. After a reset is cleared, all
registers are initialized.
Configuration mode
Reset *
1
23 clocks
Clear RSTRQ in MCR to 0
11 recessive
bits received
continuously?
Reception*
4
Transmission*
5
Normal operation
Ye s
No
Ye s
No
Clear necessary bit in
TCIMR to 0
Set PMR97 and PMR96 in
TCMR*
2
Set BCR0 and BCR1*
2
Set Mailboxes
(ID, DLC,
RTR, IDE, MBCR, DART,
LAFM, MDn0 to MDn7
[n = 0 to 3])
Notes: 1. The TinyCAN is reset at any time when the RSTRQ bit in MCR is set to 1.
2. The PMR97 and PMR96 bits in TCMR should be set after Mailboxes and LAFM have been
initialized. Then BCR1 and BVR0 should be set.
The TinyCAN starts communication with the CAN bus after BCR1 and BVR0 have been set.
3. The RESET bit in GSR is a status flag that indicates CAN bus communication is possible
after reset procedure. This bit is cleared to 0 when 23 clock cycles are elapsed after BCR0 and
BCR1 have been set.
4. The TinyCAN receives messages when MBCR and TXPR are not set.
5. When MBCR and TXPR are set, the TinyCAN starts message transmission
and carries out CAN bus arbitration. If an arbitration loss occurs, receive
operation starts.
RESET in GSR*
3
= 0?
Clear RHI in TCIRR0 to 0
Figure 15.4 Reset Clearing Flowchart