Datasheet

Section 15 Controller Area Network for Tiny (TinyCAN)
Rev. 4.00 Mar. 15, 2006 Page 325 of 556
REJ09B0026-0400
15.5.2 Bit Timing
The bit rate and bit timing are set by the bit configuration register (BCR). The CAN controllers
connected to the CAN bus should be set so that all of them have the same baud rate and same bit
width. One bit time consists of total settable Time Quantum (TQ).
SYNC_SEG PHSEG1 PHSEG2PRSEG
1 time quantum
1 bit time (8 to 25 time quanta)
Sampling point
2 to 8 time quanta4 to 16 time quanta
Time segment 1 (TSG1)
Time segment 2
(TSG2)
Figure 15.5 CAN Bit Configuration
The SYNC_SEG is a segment for establishing the synchronization of nodes on the CAN bus.
Normal bit edge changes in this segment. The PRSEG is a segment for adjusting the physical
delay between networks. The PHSEG1 is a buffer segment for adjusting positive phase drift. This
segment is extended when re-synchronization is established. The PHSEG2 is a buffer segment for
adjusting negative phase drift. This segment is shortened when re-synchronization is established.
The range of settable values in BCR (TSG1, TSG2, BRP, and SJW) is shown in table 15.2.
Table 15.2 Settable Values in BCR
Name Abbreviation Min. Value Max. Value
Time segment 1 TSG1*
1
3*
3
15
Time segment 2 TSG2*
1
1*
4
7
Baud rate prescaler BRP 1 63
Re-Synchronization Jump width SJW*
2
0 3
Notes: 1. The time quanta values for the TSEG1 and TSEG2 are as follows: TSG value + 1
2. In the CAN specifications, the Re-Synchronization Jump Width is stipulated as
4 ≥ SJW ≥ 1. The value of SJW is given by adding 1 to the setting value of the bits
SJW0 to SJW1 in BCR.
3. The minimum value of TSG1 is stipulated in the CAN specifications:
TSG1 > TSG2
4. The minimum value of TSG2 is stipulated in the CAN specifications:
TSG2 ≥ SJW