Datasheet

Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 4.00 Mar. 15, 2006 Page 349 of 556
REJ09B0026-0400
Section 16 Synchronous Serial Communication Unit (SSU)
The synchronous serial communication unit (SSU) can handle clocked synchronous serial data
communication.
Figure 16.1 shows a block diagram of the SSU.
16.1 Features
• Can be operated in clocked synchronous communication mode or four-line bus communication
mode (including bidirectional communication mode)
• Can be operated as a master or a slave device
• Choice of seven internal clocks (φ/256, φ/128, φ/64, φ/32, φ/16, φ/8, φ/4) and an external clock
as a clock source
• Clock polarity and phase of SSCK can be selected
• Choice of data transfer direction (MSB-first or LSB-first)
• Receive error detection: overrun error
• Multimaster error detection: conflict error
• Five interrupt sources: transmit-end, transmit-data-empty, receive-data-full, overrun error, and
conflict error
16.2 Continuous transmission and reception of serial data are enabled
since both transmitter and Input/Output Pins
Table 16.1 shows the pin configuration of the SSU.
Table 16.1 Pin Configuration
Pin Name Abbreviation I/O Function
SSU clock SSCK I/O SSU clock input/output
SSU data input/output SSI I/O SSU data input/output
SSU data input/output SSO I/O SSU data input/output
SSU chip select input/output SCS I/O SSU chip select input/output