Datasheet

Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 4.00 Mar. 15, 2006 Page 351 of 556
REJ09B0026-0400
16.3.1 SS Control Register H (SSCRH)
SSCRH is a register that selects a master or a slave device, enables bidirectional mode, selects
open-drain output of the serial data output pin, selects an output value of the serial data output pin,
selects the SSCK pin, and selects the SCS pin.
Bit Bit Name
Initial
Value R/W Description
7 MSS 0 R/W Master/Slave Device Select
Selects whether this module is used as a master device
or a slave device. When this module is used as a master
device, transfer clock is output from the SSCK pin. When
the CE bit in SSSR is set, this bit is automatically cleared.
0: Operates as a slave device
1: Operates as a master device
6 BIDE 0 R/W Bidirectional Mode Enable
Selects whether the serial data input pin and the output
pin are both used or only one pin is used. For details,
refer to section 16.4.3, Relationship between Data
Input/Output Pin and Shift Register. When the SSUMS bit
in SSCRL is 0, this setting is invalid.
0: Normal mode. Communication is performed by using
two pins.
1: Bidirectional mode. Communication is performed by
using only one pin.
5 SOOS 0 R/W Serial Data Open-Drain Output Select
Selects whether the serial data output pin is CMOS
output or NMOS open-drain output. The serial data output
pin is changed according to the register setting value. For
details, refer to section 16.4.3, Relationship between
Data Input/Output Pin and Shift Register.
0: CMOS output
1: NMOS open-drain output