Datasheet

Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 4.00 Mar. 15, 2006 Page 353 of 556
REJ09B0026-0400
16.3.2 SS Control Register L (SSCRL)
SSCRL is a register that controls module standby, mode, and software reset and selects open-drain
output of the SSCK and SCS pins.
Bit Bit Name
Initial
Value R/W Description
7 MSTSSU 0 R/W SSU Module Standby
When this bit is 1, the SSU enters the module standby
state. In the module standby state, the SSU internal
registers other than SSCRL cannot be written to.
6 SSUMS 0 R/W SSU Mode Select
Selects which combination of the serial data input pin and
serial data output pin is used.
For details, refer to section 16.4.3, Relationship between
Data Input/Output Pin and Shift Register.
0: Clocked synchronous communication mode
Data input: SSI pin, Data output: SSO pin
1: Four-line bus communication mode
When MSS = 1 and BIDE = 0 in SSCRH:
Data input: SSI pin, Data output: SSO pin
When MSS = 0 and BIDE = 0 in SSCRH:
Data input: SSO pin, Data output: SSI pin
When BIDE = 1 in SSCRH:
Data input and output: SSO pin
5 SRES 0 R/W Software reset
When this bit is set to 1, the SSU internal sequencer is
forcibly reset. Then this bit is automatically cleared. The
register value in the SSU is retained.
4 SCKOS 0 R/W SSCK Pin Open-Drain Output Select
Selects whether the SSCK pin functions as CMOS output
or NMOS open-drain output.
0: CMOS output
1: NMOS open-drain output