Datasheet

Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 4.00 Mar. 15, 2006 Page 354 of 556
REJ09B0026-0400
Bit Bit Name
Initial
Value R/W Description
3 CSOS 0 R/W SCS Pin Open-Drain Output Select
Selects whether the SCS pin functions as CMOS output
or NMOS open-drain output.
0: CMOS output
1: NMOS open-drain output
2 to 0  All 0  Reserved
These bits are always read as 0.
16.3.3 SS Mode Register (SSMR)
SSMR is a register that selects MSB-first or LSB-first, clock polarity, clock phase, and transfer
clock rate.
Bit Bit Name
Initial
Value R/W Description
7 MLS 0 R/W MSB-First/LSB-First Select
Selects whether data transfer is performed in MSB-first or
LSB-first.
• 0: LSB-first
• 1: MSB-first
6 CPOS 0 R/W Clock Polarity Select
Selects the clock polarity of SSCK.
0: Idle state = high
1: Idle state = low
5 CPHS 0 R/W Clock Phase Select
Selects the clock phase of SSCK.
0: Data change at first edge
1: Data latch at first edge
4, 3  All 0  Reserved
These bits are always read as 0.