Datasheet

Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 4.00 Mar. 15, 2006 Page 355 of 556
REJ09B0026-0400
Bit Bit Name
Initial
Value R/W Description
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Transfer clock rate select
Sets transfer clock rate (prescaler division ratio) when the
internal clock is selected.
000: φ/256
001: φ/128
010: φ/64
011: φ/32
100: φ/16
101: φ/8
110: φ/4
111: Reserved
16.3.4 SS Enable Register (SSER)
SSER is a register that sets transmit enable, receive enable, and interrupt enable.
Bit Bit Name
Initial
Value R/W Description
7 TE 0 R/W Transmit enable
When this bit is 1, transmit operation is enabled.
6 RE 0 R/W Receive enable
When this bit is 1, receive operation is enabled.
5 RSSTP 0 R/W Receive single stop
When this bit is 1, receive operation is completed after
receiving one byte.
4 — 0 — Reserved
This bit is always read as 0.
3 TEIE 0 R/W Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
2 TIE 0 R/W Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.