Datasheet

Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 4.00 Mar. 15, 2006 Page 356 of 556
REJ09B0026-0400
Bit Bit Name
Initial
Value R/W Description
1 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, an RXI and an OEI interrupt
requests are enabled.
0 CEIE 0 R/W Conflict Error Interrupt Enable
When this bit is set to 1, a CEI interrupt request is
enabled.
16.3.5 SS Status Register (SSSR)
SSSR is a register that sets interrupt flags.
Bit Bit Name
Initial
Value R/W Description
7 — 0 — Reserved
This bit is always read as 0.
6 ORER 0 R/W Overrun Error Flag
Indicates that the RDRF bit is abnormally terminated in
reception because an overrun error has occurred.
SSRDR retains received data before the overrun error
occurs and the received data after the overrun error
occurs is lost. When this bit is set to 1, subsequent serial
reception cannot be continued. When the MSS bit in
SSCRH is 1, this is also applied to serial transmission.
[Setting condition]
• When the next serial reception is completed while
RDRF = 1
[Clearing condition]
• When 0 is written to this bit after reading 1
5, 4  All 0  Reserved
These bits are always read as 0.