Datasheet

Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 4.00 Mar. 15, 2006 Page 376 of 556
REJ09B0026-0400
16.4.10 SCS Pin Control and Arbitration
When the SSUMS bit in SSCRL is set to 1 and the CSS1 bit in SSCRH is set to 1, the MSS bit in
SSCRH is set to 1 and then the arbitration of the SCS pin is checked before starting serial transfer.
If the SSU detects that the synchronized internal SCS pin goes low in this period, the CE bit in
SSSR is set and the MSS bit is cleared.
Note: When a conflict error is set, subsequent transmit operation is not possible. Therefore the
CE bit must be cleared to 0 before starting transmission.
When the multimaster error is used, the CSOS bit in SSCRL should be set to 1.
MSS
Transfer start
Write data
in SSTDR
Arbitration detection
period
Maximum time of SCS internal synchronization
Internal SCS
(synchronized)
SCS input
SCS output
CE
Figure 16.13 Arbitration Check Timing