Datasheet

Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 4.00 Mar. 15, 2006 Page 377 of 556
REJ09B0026-0400
16.4.11 Interrupt Requests
The SSU has five interrupt requests: transmit data empty, transmit end, receive data full, overrun
error, and conflict error. Since these interrupt requests are assigned to the common vector address,
interrupt sources must be determined by flags. Table 16.3 lists the interrupt requests.
Table 16.3 Interrupt Requests
Interrupt Request Abbreviation Interrupt Condition
Transmit data empty TXI (TIE = 1), (TDRE = 1)
Transmit end TEI (TEIE = 1), (TEND = 1)
Receive data full RXI (RIE = 1), (RDRF = 1)
Overrun error OEI (RIE = 1), (ORER = 1)
Conflict error CEI (CEIE = 1), (CE = 1)
When an interrupt condition shown in table 16.3 is 1 and the I bit in CCR is 0, the CPU executes
the interrupt exception handling. Each interrupt source must be cleared during the exception
handling. Note that the TDRE and TEND bits are automatically cleared by writing transmit data in
SSTDR and the RDRF bit is automatically cleared by reading SSRDR. When transmit data is
written in SSTDR, the TDRE bit is set again at the same time. Then if the TDRE bit is cleared,
additional one byte of data may be transmitted.