Datasheet

Section 17 Subsystem Timer (Subtimer)
Rev. 4.00 Mar. 15, 2006 Page 381 of 556
REJ09B0026-0400
17.2 Register Descriptions
The subtimer has the following registers.
• Subtimer control register (SBTCTL)
• Subtimer counter (SBTDCNT)
• Ring oscillator prescaler setting register (ROPCR)
17.2.1 Subtimer Control Register (SBTCTL)
SBTCTL controls oscillation of the on-chip oscillator, subclock output, and counter operation and
indicates the operating state. SBTCTL is initialized to H'60.
Bit Bit Name
Initial
Value R/W Description
7 PCEF 0 R/W Division Count End Flag
[Setting condition]
When counting starts at the first falling edge and SBTPS
halts at the third falling edge after the on-chip oscillator
starts oscillation.
[Clearing condition]
When 0 is written to this bit after reading 1
6, 5  All 1  Reserved
These bits are always read as 1.
4 START 0 R/W Count Down Start
Starts or halts the SBTDCNT operation.
0: SBTDCNT halts counting down.
1: SBTDCNT starts counting down.
3 OSCEB 0 R/W On-Chip Oscillator Oscillation Enable
Enables or disables the oscillation of the on-chip
oscillator.
0: Oscillation of on-chip oscillator is disabled.
1: Oscillation of on-chip oscillator is enabled.