Datasheet

Section 17 Subsystem Timer (Subtimer)
Rev. 4.00 Mar. 15, 2006 Page 383 of 556
REJ09B0026-0400
17.3 Operation
17.3.1 SBTPS Division Ratio Setting
The oscillation frequency of the on-chip oscillator ranges from 64 kHz to 850 kHz. To make a
subclock with expected frequency by dividing the oscillation frequency, ROPCR must be
configured by using following (1) to (6) formulas. The SBTPS division ratio is set as follows.
1. When the OSCEB bit in SBTCTL is set to 1, SBTPS counts two system clock cycles from the
first falling edge of PSCIN to the third falling edge.
2. SBTPS halts counting at the third falling edge of PSCIN, the PCEF flag in SBTCTL is set to 1,
and then the SBTPS value is transferred to ROPCR.
3. By using this count value, the division ratio of the on-chip oscillator is determined and the
value is set in ROPCR.
4. SBTPS starts supplying clocks and SBTDCNT starts counting down by clearing the PCEF flag
in SBTCTL to 0.
mH'FF n
PCEF flag
ROPCR
PSCIN
2T
RO
OSCEB is set
ROPCR is set
SBTPS counting halts
PCEF is set
Count value is transferred
to ROPCR
PCEF is cleared
Supplying subclocks starts
SBTDCNT counting starts
Subclock (φw)
System clock (φ)
t
Figure 17.2 Timing for On-Chip Oscillator