Datasheet

Section 17 Subsystem Timer (Subtimer)
Rev. 4.00 Mar. 15, 2006 Page 385 of 556
REJ09B0026-0400
• Subclock error
In addition to the above rounding error, the subtimer may have a count error caused by time
lag between the system clock and the on-chip oscillator. The example is shown below.
Table 17.1 Example of Subclock Error
Condition: System clock = 10 MHz, on-chip oscillator = 400 kHz, and subclock = 12 kHz
Min. Expected Value Max.
Count Value n 49 50 51
Division ratio k 34 33 33
Rounding error of
division ratio σ
 +1.0 % 
Rounding error of
division ratio σ + count
error
−2.0 %  +1.0 %
After deciding the division ratio according to formulas (1) to (3), the division ratio is
configured in ROPCR. After ROPCR divides clocks of the on-chip oscillator, clocks for the
subtimer counter, input clocks to the system, and input clocks to the watchdog timer are
generated.
Yes
No
Set OSCEB bit in SBTCTL to 1
PCEF flag in SBTCTL = 1?
Calculate division ratio
Write calculated division ratio in ROPCR
Clear PCEF flag in SBTCTL to 0
Start configuration of division ratio
Configuration of division ratio completed
Figure 17.3 SBTPS Setting Flowchart