Datasheet

Section 17 Subsystem Timer (Subtimer)
Rev. 4.00 Mar. 15, 2006 Page 387 of 556
REJ09B0026-0400
17.4 Count Operation
The subtimer has an 8-bit readable/writable down counter, SBTDCNT. When any value ranging
from H′00 to H′FF is written to SBTDCNT and the START bit in SBTCTL is set to 1, the
subtimer starts counting down from the configured value in SBTDCNT. When an underflow
occurs at H'00, the subtimer requests an interrupt to the CPU. At the end of the exception
handling, the subtimer starts counting down again from the configured value written in
SBTDCNT. If another value is written in SBTDCNT, the subtimer starts counting down from the
rewritten value. Therefore, the underflow cycle can be set in the range from 1 to 256 input clocks
according to the configured value in SBTDCNT. Figure 17.4 shows an example of the subtimer
operation and figure 17.5 shows the flowchart.
Clocks are supplied to the entire chip by setting the SYSCKS bit in SBTCTL to 1. When the
SYSCKS bit is cleared to 0, clock supply to the entire chip is disabled and only the subtimer
operates.
(Example) When φ is 32 kHz and the underflow cycle is 100 ms:
= 25
128
32
× 10
3
× 100 × 10
-3
Therefore, set 25 (H′19) in SBTDCNT.